WIRING BOARD
A wiring board of the present invention includes a core substrate, insulating layers laminated on upper and lower surfaces of the core substrate, and a conductor layer deposited on the upper and lower surfaces of the core substrate and a surface of each of the insulating layers, in such a manner as to make a difference in area occupation ratio between the upper and lower surfaces of the core substrate. A thickness of a conductor that has a large area occupation ratio is smaller than a thickness of a conductor that has a small area occupation ratio between the conductor layers deposited on the upper and lower surfaces of the core substrate, and between the conductor layers deposited on the surface of each of the insulating layers laminated at an identical level on upper and lower surface sides with the core substrate as a center.
1 . A wiring board comprising:
a core substrate;
insulating layers laminated with an identical number of layers on upper and lower surfaces of the core substrate; and
a conductor layer deposited on the upper and lower surfaces of the core substrate and a surface of each of the insulating layers respectively laminated on the upper and lower surfaces of the core substrate, in such a manner as to make a difference in area occupation ratio between the upper and lower surfaces of the core substrate,
wherein a thickness of a conductor that has a large area occupation ratio is smaller than a thickness of a conductor that has a small area occupation ratio between the conductor layers deposited on the upper and lower surfaces of the core substrate, and between the conductor layers deposited on the surface of each of the insulating layers laminated at an identical level on upper and lower surface sides with the core substrate as a center.
2 . The wiring board according to claim 1 , wherein the insulating layers are laminated in a two-layer structure on upper and lower surfaces of the core substrate.
3 . The wiring board according to claim 1 , wherein the thickness of the conductor having the large area occupation ratio is 3 to 5 μm smaller than the thickness of the conductor having the small area occupation ratio.