LAYERED ACTIVE REGION LIGHT EMITTING DIODE
An apparatus includes a p-type semiconductor material, an n-type semiconductor material, and an active region disposed between the p-type semiconductor material and the n-type semiconductor material. The active region emits light in response to a voltage applied across the active region, and the active region includes a quantum well region, a barrier region, and a capping region. The barrier region is disposed to confine charge carriers in the quantum well region. The capping region is disposed between the quantum well region and the barrier region, and the capping region is adjacent to the quantum well region to stabilize a material composition of the quantum well region. The quantum well region, the barrier region, and the capping region collectively form a first tri-layer structure.
1 . An apparatus, comprising:
a p-type semiconductor material;
an n-type semiconductor material; and
an active region disposed between the p-type semiconductor material and the n-type semiconductor material, wherein the active region emits light in response to a voltage applied across the active region, and wherein the active region includes:
a quantum well region;
a barrier region disposed to confine charge carriers in the quantum well region; and
a capping region disposed between the quantum well region and the barrier region, wherein the capping region is adjacent to the quantum well region to stabilize a material composition of the quantum well region, and wherein the quantum well region, the barrier region, and the capping region collectively form a first tri-layer structure.
2 . The apparatus of claim 1 , wherein the quantum well region includes InGaN, the capping region includes AlGaN, and the barrier region includes (AlIn)GaN.
3 . The apparatus of claim 1 , wherein the active region includes a plurality of quantum well regions, a plurality of barrier regions, and a plurality of capping regions.
4 . The apparatus of claim 3 , further comprising a plurality of tri-layer structures, wherein the barrier region of the first tri-layer structure contacts a quantum well region of a second tri-layer structure.
5 . The apparatus of claim 1 , wherein a lateral diameter of the active region is less than 100 μm.
6 . The apparatus of claim 1 , wherein the p-type semiconductor material includes GaN and the n-type semiconductor material includes GaN.
7 . The apparatus of claim 1 , further comprising an electron blocking layer disposed between the active region and the p-type semiconductor material.
8 . The apparatus of claim 1 , wherein the active region is included in a first light emitting diode (LED) in a plurality of LEDs, and wherein the plurality of LEDs are arranged into an array and communicatively coupled to a display module.
9 . The apparatus of claim 8 , wherein the display module is coupled to control logic to control operation of the plurality of LEDs.
10 . The apparatus of claim 1 , further comprising a first electrode and a second electrode, wherein the first electrode is coupled to the p-type semiconductor material and the second electrode is coupled to the n-type semiconductor material, and wherein at least one of the first electrode and second electrode is transparent.
11 . The apparatus of claim 10 , wherein the p-type semiconductor material, the n-type semiconductor material, and active layer are disposed between the first electrode and the second electrode.
12 . A method of fabricating a light emitting diode (LED), comprising:
forming a first semiconductor material of a first majority charge carrier type on a first side of a release layer, wherein a second side of the release layer is disposed over a substrate;
depositing an active region on the first semiconductor material, wherein the active region includes:
a quantum well region, a barrier region, and a capping region, wherein the quantum well region, the barrier region, and the capping region form a first tri-layer structure; and
depositing a second semiconductor material of a second majority charge carrier type, wherein the second majority charge carrier type is opposite the first majority charge carrier type, and wherein the active region is disposed between the first semiconductor material and the second semiconductor material; and
removing the release layer to release the first semiconductor material, the second semiconductor material, and the active region from the substrate.
13 . The method of claim 12 , wherein the quantum well region includes InGaN, the capping region includes AlGaN, the barrier region includes (In)GaN, and the release layer includes InGaN:Si.
14 . The method of claim 12 , wherein depositing the active region includes forming plurality of quantum well regions, a plurality of barrier regions, and a plurality of capping regions.
15 . The method of claim 14 , wherein depositing the active region includes forming a plurality of tri-layer structures, wherein the barrier region of the first tri-layer structure contacts the quantum well region of a second tri-layer structure, and wherein the quantum well region is disposed between the barrier region and the capping region.
16 . The method of claim 12 , further comprising forming a semiconductor layer between the substrate and the release layer.
17 . The method of claim 12 , further comprising forming an electron blocking layer disposed between the active region and the second semiconductor material.
18 . The method of claim 17 , wherein the electron blocking layer includes Al(In)GaN.
19 . The method of claim 12 , wherein forming the first semiconductor material and the second semiconductor material includes depositing GaN.
20 . The method of claim 12 , further comprising forming a first electrode and a second electrode, wherein the first electrode is coupled to the first semiconductor material and the second electrode is coupled to the second semiconductor material.