Detection circuit
View Patent ↗Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.
1. A detection circuit, comprising:
a voltage input terminal;
a voltage output terminal;
an output transistor connected between the voltage input terminal and the voltage output terminal;
a control circuit configured to control the output transistor; and
a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal and comprising a comparator which outputs a signal indicating detection of the open-circuit of the load;
wherein an output circuit of the load open-circuit detection circuit comprises a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate connected to the comparator and controlled to be turned on or off by the comparator, the gate of the second transistor connected to the gate of the first transistor in series; and
wherein the first transistor is in an off state when the output transistor is in an off state.
2. A detection circuit according to claim 1 , further comprising a third transistor that is connected in parallel to the first transistor, and is controlled by the control circuit.
3. A detection circuit, comprising:
a voltage input terminal;
a voltage output terminal;
an output transistor connected between the voltage input terminal and the voltage output terminal;
a control circuit configured to control the output transistor; and
a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal,
wherein an output circuit of the load open-circuit detection circuit comprises a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and
wherein the first transistor is in an off state when the output transistor is in an off state;
wherein the first transistor comprises one of a transistor having the same type and the same threshold as the output transistor, and a transistor having a threshold higher than a threshold of the output transistor.
4. A detection circuit, comprising:
a voltage input terminal;
a voltage output terminal;
an output transistor connected between the voltage input terminal and the voltage output terminal;
a control circuit configured to control the output transistor; and
a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal,
wherein an output circuit of the load open-circuit detection circuit comprises a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and
wherein the first transistor is in an off state when the output transistor is in an off state;
wherein a gate of the output transistor and the gate of the first transistor are connected to each other via a voltage level shift stage.
5. A detection circuit according to claim 4 , wherein the voltage level shift stage is a source follower amplifier stage.