IP Library Granted Patent US 9,571,094
Granted Patent B2
US 9,571,094 · App. 15/002,693 · Granted Feb 14, 2017

Switch circuit

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Quick Facts
Patent No.
US 9,571,094
App. No.
15/002,693
Granted
Feb 14, 2017
Kind
B2
Abstract

To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even when a positive or negative voltage is inputted to an input terminal, and thereby reduces the risk of latch-up. A switch circuit is comprised of NMOS transistors, and the gates of the NMOS transistors are controlled by an output voltage of a boosting circuit, thereby making it possible to reliably control transmission or shut-off of a voltage from GND to VDD.

Claims (11)

1. A switch circuit provided at an input terminal of a semiconductor device, which is inputted with a positive or negative voltage, and controlling whether to transmit the positive or negative voltage to an internal circuit or shut off the positive or negative voltage, said switch circuit comprising:

a first NMOS transistor having a drain connected to the input terminal of the semiconductor device, a source connected to a first node, and a gate connected to a second node;

a second NMOS transistor having a drain connected to the first node, a source connected to a third node, and a gate connected to the second node;

a third NMOS transistor having a source connected to a ground voltage, a drain connected to the first node, a gate connected to a switch control terminal via an inverter; and

a boosting circuit having a boosting circuit control terminal connected to the switch control terminal, a voltage input terminal connected to a power supply, and a voltage output terminal connected to the second node, wherein the boosting circuit comprises:

a rectifying element having an anode connected to the voltage input terminal and a cathode connected to a fourth node,

a PMOS transistor having a drain connected to the voltage output terminal, a gate connected to the switch control terminal via the inverter, and source connected to the fourth node,

a fourth NMOS transistor having a drain connected to the voltage output terminal, a gate connected to the switch control terminal via the inverter, and a source connected to the ground voltage, and

a capacitor having one end connected to the fourth node and the other end connected to the boosting circuit control terminal;

wherein the third node is connected to the internal circuit.

2. The switch circuit according to claim 1 , including a voltage limiting circuit having one end connected to the second node and the other end connected to the ground voltage.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2016
From: HIRAOKA, NAOHIRO; OKA, TOMOHIRO
To: SEIKO INSTRUMENTS INC.
Reel/Frame 037552/0387 →