Semiconductor memory device and data writing method using a checkerboard pattern utilizing existing data supply bit addresses
View Patent ↗To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.
1. A semiconductor memory device comprising:
a memory array which has a plurality of memory words each comprised of a plurality of memory cell groups and one word selector and in which the memory words pairs adjacent in a row direction are respectively to be first reversedly disposed with a column direction as an axis, the memory words pairs adjacent in the column direction are respectively to be second reversedly disposed with the row direction as an axis, and the memory words pairs are arranged in a matrix form;
a data supply means which is connected to the memory array and supplies writing data corresponding to one word;
an address counter which holds an address for selecting a specific word in the memory array;
a row decoder connected to the address counter and capable of performing a functional switching to one-row selection, even row batch selection, odd row batch selection, and all row batch selection modes;
a column decoder connected to the address counter and capable of performing the functional switching to one-column selection, even column batch selection, odd column batch selection, and all column batch selection modes; and
a control circuit which controls the functional switching of the column decoder and the row decoder.
2. A data writing method comprising the steps of in the semiconductor memory device according to claim 1 :
selecting all row batch selection and all column batch selection modes and writing data of patterns in each of which data of memory cells adjacent in each memory word pairs are inverted, into all memory words;
subsequently selecting an even or odd row batch selection mode and an even or odd column batch selection mode and writing data of a pattern reverse to each of the patterns subjected to the inversion into a selected memory word; and
further selecting an odd or even row batch selection mode and an odd or even column batch selection mode both unselected in the even or odd row batch selection mode and the even or odd column batch selection mode, and writing data of a same pattern as a pattern in reverse to the pattern subjected to the inversion into a selected memory word.