Array substrate, display panel and display apparatus

1. A thin-film transistor (TFT) array substrate, comprising:

a substrate having at least a display region;

a plurality of top-gated thin-film transistors formed over the substrate;

a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality of pre-reserved blank regions are configured among the scan lines, the data lines, and the plurality of sub-pixels in the display region; and

a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.

2. The thin-film transistor (TFT) array substrate according to claim 1 , wherein a top-gated thin-film transistors further comprise:

a semiconductor layer formed over the substrate;

a gate metal layer formed over the semiconductor layer; and

a source and drain metal layer formed over the gate mater layer.

3. The thin-film transistor (TFT) array substrate according to claim 2 , further comprising:

a first non-conductive dielectric layer formed over the source and drain metal layer;

a common electrode layer formed over the first non-conductive dielectric layer; and

a pixel electrode layer formed over the common electrode layer,

wherein the common electrode layer covers the gate drive circuit.

4. The thin-film transistor (TFT) array substrate according to claim 2 , wherein:

the semiconductor layer is made of polycrystalline silicon.

5. The thin-film transistor (TFT) array substrate according to claim 2 , wherein the display region further comprises:

a plurality of pixel cells,

wherein:

each of the plurality of pixel cells includes a first sub-pixel and an adjacent second sub-pixel of the plurality of sub-pixels;

a first data line and a second data line of the plurality of data lines are disposed between the first sub-pixel and the second sub-pixel; and

the first sub-pixel and the second sub-pixel are connected to the first data line and the second data line, respectively.

6. The thin-film transistor (TFT) array substrate according to claim 5 , wherein a pre-reserved blank region further comprises:

a first pre-reserved blank region between two adjacent pixel cells, extending along a direction of the data lines; and

a second pre-reserved blank region between the first data line and the second data line, extending along the direction of the data lines.

7. The thin-film transistor (TFT) array substrate according to claim 6 , wherein:

a plurality of sub-pixels in a same row are connected to a same scan line,

wherein the display region further comprises:

a plurality of third sub-pixels of the plurality of sub-pixels and a plurality of fourth sub-pixels of the plurality of sub-pixels, connecting to a first scan line of the plurality of scan lines and a second scan line of the plurality of scan lines, disposed between the first scan lines and the second scan lines, respectively.

8. The thin-film transistor (TFT) array substrate according to claim 7 , the pre-reserved blank region further comprises:

a third pre-reserved blank region disposed between the first scan line and the third sub-pixel region, extending along a direction of the scan lines;

a fourth pre-reserved blank region disposed between the second scan line and the fourth sub-pixel, extending along the direction of the scan lines; and

a fifth pre-reserved blank region disposed between the first scan line and the fourth sub-pixel, extending along the direction of the scan lines.

9. The thin-film transistor (TFT) array substrate according to claim 8 , the gate driver circuit further comprises at least:

a signal control line;

a top-gated thin-film transistor (TFT); and

a capacitor.

10. The thin-film transistor (TFT) array substrate according to claim 9 , wherein the signal control line further comprises:

a first signal wiring formed by patterning the gate metal layer; and

a second signal wiring formed by patterning the source and drain metal layer,

wherein the first signal wiring and the second signal wiring are electrically connected by a first through-hole structure.

11. The thin-film transistor (TFT) array substrate according to claim 10 , wherein the signal control line further comprises:

a signal control line group including at least two signal control lines electrically connected in parallel through at least a first connecting wiring, and disposed in different first pre-reserved blank regions.

12. The thin-film transistor (TFT) array substrate according to claim 9 , wherein the top-gated thin-film transistor further comprises:

a first semiconductor formed by patterning the semiconductor layer;

a gate facing the first semiconductor formed by patterning the gate metal layer;

a source formed by patterning the source and drain metal layer; and

a drain formed by patterning the source and drain metal layer.

13. The thin-film transistor (TFT) array substrate according to claim 12 , wherein:

the first semiconductor is disposed in an overlapping region of the first pre-reserved blank region and the fifth pre-reserved region;

the source includes a first source wiring disposed in parallel with the data lines and a second source wiring disposed in parallel with the scan lines,

wherein:

the first source wiring is formed by patterning the source and drain metal layer, and disposed in the first pre-reserved blank region;

the second source wiring is formed by patterning the gate metal layer, and disposed in the third pre-reserved blank region; and

the first source wiring and the second source wiring are electrically connected through a second through-hole structure;

and

the drain includes a first drain wiring disposed in parallel with the data lines and a second drain wiring disposed in parallel with the scan lines,

wherein:

the first drain wiring is formed by patterning the source and drain metal layer, and disposed in the first pre-reserved blank region;

the second drain wiring is formed by patterning the gate metal layer, and disposed in one of the fourth pre-reserved blank region and a second fifth pre-reserved blank region; and

the first drain wiring and the second wiring are electrically connected through a third through-hole structure.

14. The thin-film transistor (TFT) array substrate according to claim 12 , wherein:

the first semiconductor is disposed in an overlapping region of the first pre-reserved blank region and the fourth pre-reserved region;

the source includes a first source wiring disposed in parallel to the data lines, and a second source wiring disposed in parallel to the scan lines,

wherein:

the first source wiring is formed by patterning the source and drain metal layer, and disposed in the first pre-reserved blank region;

the second source wiring is formed by patterning the gate metal layer, and disposed in the fifth pre-reserved blank region; and

the first source wiring and the second source wiring are electrically connected through a second through-hole structure;

and

the drain includes a first drain wiring disposed in parallel to the data line, and a second drain wiring disposed in parallel to the scan line,

wherein:

the first drain wiring is formed by patterning the source and drain metal layer, and disposed in the first pre-reserved blank region;

the second drain wiring is formed by patterning the gate metal layer, and disposed in a second fifth pre-reserved blank region; and

the first drain wiring and the second drain wiring are electrically connected through a third through-hole structure.

15. The thin-film transistor (TFT) array substrate according to claim 13 , wherein the gate driver circuit further comprises at least:

a thin-film transistor (TFT) group having a plurality of thin-film transistors (TFTs) connected in parallel, and disposed in different pre-reserved blank regions.

16. The thin-film transistor (TFT) array substrate according to claim 13 , wherein the thin film transistor further comprises:

diode-type thin film transistors (TFTs) formed by one of short-circuiting the sources and the gates of the thin-film transistors (TFTs), and short-circuiting the drains and the gates of the thin-film transistors (TFTs).

17. The thin-film transistor (TFT) array substrate according to claim 9 , wherein the capacitor further comprises:

a first capacitor electrode disposed in the first pre-reserved blank region; and

a second capacitor electrode facing the first capacitor electrode disposed in the first pre-reserved blank region.

18. The thin-film transistor (TFT) array substrate according to claim 17 , wherein the second capacitor electrode further comprises:

a first extending electrode.

19. A display panel comprising at least a thin-film transistor (TFT) array substrate according to claim 1 .

20. A display apparatus comprising at least a display panel according to claim 19 .