Dynamic memory reallocation for match-action packet processing
View Patent ↗A pool of unit memories is provided in order to flexibly allocate memory capacity to implement various tables and/or logical memories such as those for implementing an OpenFlow switch. The pool is structured with routing resources for allowing flexible allocation and reallocation of memory capacity to the various tables. The unit memories and logical units in the pool are interconnected by a set of horizontal routing resources and a set of vertical routing resources.
1. A method comprising:
configuring a pool of unit memories for implementing a plurality of tables, wherein each table is allocated a unique set of the unit memories, said configuring constrained by a first set of constraints for using routing resources in the pool;
receiving packets and computing packet forwarding decisions based on data from the received packets and data stored in each table; and
reconfiguring the pool of unit memories in order to re-allocate a unit memory from a first table to a second table while using said tables to compute packet forwarding decisions, said reconfiguring constrained by a second set of constraints for using routing resources in the pool.
2. The method of claim 1 , wherein the pool of unit memories is organized into a plurality of rows, wherein re-allocating a unit memory comprises moving the content of a unit memory at a first row to a unit memory at a second row that is different from the first row.
3. The method of claim 2 , where each table is further allocated a logical unit, wherein the logical unit has direct access to unit memories in one of the rows.
4. The method of claim 3 , where configuring the pool of unit memories comprises configuring the routing resources of the pool to provide the allocated logical unit of each table unobstructed access to each allocated unit memory of the table.
5. The method of claim 1 , wherein the routing resource of the pool comprises a first set of routing resources and a second set of routing resources, where the first set of constraints limits the plurality of tables to using the first set of routing resources but not the second set of routing resources.
6. The method of claim 5 , wherein the second set of constraints limits the plurality of tables to using the first set of routing resources and the second set of routing resources.
7. The method of claim 5 , wherein the pool of unit memories is organized into a plurality of rows and each row is associated with a logical unit, wherein the first set of routing resources comprises a first vertical routing bus for allowing a logical unit to access unit memories at rows above the logical unit.
8. The method of claim 7 , wherein the second set of routing resources comprises a second routing bus for allowing the logical unit to access unit memories at rows below the logical unit.
9. A method comprising:
configuring a pool of unit memories for implementing a plurality of tables, wherein each table is allocated a unique set of the unit memories, said configuring constrained by a first set of constraints for using routing resources in the pool;
copying content of a first unit memory to a second unit memory, wherein the first unit memory is allocated to a first table; and
reconfiguring the pool of unit memories in order to allocate the second unit memory to the first table and to reallocate the first unit memory to a second table, said reconfiguring constrained by a second set of constraints for using routing resources in the pool.
10. The method of claim 9 , wherein the routing resource of the pool comprise a first set of routing resources and a second set of routing resources, where the first set of constraints limits the plurality of tables to using the first set of routing resources but not the second set of routing resources.
11. The method of claim 10 , wherein the second set of constraints limits the plurality of tables to using the first set of routing resources and the second set of routing resources.
12. The metod of claim 10 , wherein the pool of unit memories is organized into a plurality of rows and each row is associated with a logical unit, wherein the first set of routing resources comprises a first vertical routing bus for allowing a logical unit to access unit memories at rows above the logical unit.