IP Library Granted Patent US 9,563,484
Granted Patent B2
US 9,563,484 · App. 15/007,836 · Granted Feb 7, 2017

Concurrent computing with reduced locking requirements for shared data

Inventor: Daniel M. Yellin (Raanana, IL)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F9/526G06F9/4881G06F9/50G06F9/5016G06F9/52G06F9/528
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Quick Facts
Patent No.
US 9,563,484
App. No.
15/007,836
Granted
Feb 7, 2017
Kind
B2
Abstract

Where data are shared by multiple computer processing threads, modifying the data by determining whether modifying data associated with a first computer processing thread violates a constraint associated with the data, and responsive to determining that modifying the data associated with the computer processing thread violates the constraint associated with the data, using the data associated with the first computer processing thread to modify the data shared by the multiple computer processing threads that includes the first computer processing thread, where the constraint associated with the data associated with the first computer processing thread represents a portion of a tolerance value that is associated with the data shared by the multiple computer processing threads and that is divided among multiple constraints, where each of the constraints is associated with a different one of the multiple computer processing threads.

Claims (55)

1. A computer-implemented method, comprising:

determining whether modifying data associated with a first computer processing thread violates a constraint associated with the data; and

using, responsive to a determination that the modifying the data violates the constraint associated with the data, the data to modify data shared by multiple computer processing threads that includes the first computer processing thread, wherein

the constraint represents a portion of a tolerance value that is

a) associated with the data shared by the multiple computer processing threads and

b) divided among a plurality of constraints and each of the plurality of constraints is associated with a different one of the multiple computer processing threads.

2. The method of claim 1 , further comprising:

configuring a set of computer software instructions to perform the determining and the using.

3. The method of claim 2 , further comprising:

causing each of the multiple computer processing threads to execute a different instance of the computer software instructions.

4. The method of claim 1 , wherein

the data shared by the multiple computer processing threads is a single numeric value.

5. The method of claim 1 , wherein

the data shared by the multiple computer processing threads is a set of multiple elements.

6. The method of claim 1 , wherein

each of the multiple computer processing threads has an associated own thread-local data for storing modifications intended for the data shared by the multiple computer processing thread.

7. A computer hardware system, comprising:

at least one hardware processor configured to initiate the following executable operations:

determining whether modifying data associated with a first computer processing thread violates a constraint associated with the data; and

using, responsive to a determination that the modifying the data violates the constraint associated with the data, the data to modify data shared by multiple computer processing threads that includes the first computer processing thread, wherein

the constraint represents a portion of a tolerance value that is

a) associated with the data shared by the multiple computer processing threads and

b) divided among a plurality of constraints and each of the plurality of constraints is associated with a different one of the multiple computer processing threads.

8. The system of claim 7 , wherein the at least one hardware processor is further configured to initiate the following executable operation:

configuring a set of computer software instructions to perform the determining and the using.

9. The system of claim 8 , wherein the at least one hardware processor is further configured to initiate the following executable operation:

causing each of the multiple computer processing threads to execute a different instance of the computer software instructions.

10. The system of claim 7 , wherein

the data shared by the multiple computer processing threads is a single numeric value.

11. The system of claim 7 , wherein

the data shared by the multiple computer processing threads is a set of multiple elements.

12. The system of claim 7 , wherein

each of the multiple computer processing threads has an associated own thread-local data for storing modifications intended for the data shared by the multiple computer processing thread.

13. The system of claim 7 , wherein the at least one hardware processor is further configured to initiate the following executable operation:

modifying the data associated with the first computer processing thread with a modification intended for the data shared by the multiple computer processing threads upon a determination that the modification does not violate the constraint.

14. A computer program product, comprising:

a hardware storage device having stored therein computer-readable program code for testing a computer software application,

the computer-readable program code, when executed by a computer hardware system, causes the computer hardware system to perform:

determining whether modifying data associated with a first computer processing thread violates a constraint associated with the data; and

using, responsive to a determination that the modifying the data violates the constraint associated with the data, the data to modify data shared by multiple computer processing threads that includes the first computer processing thread, wherein

the constraint represents a portion of a tolerance value that is

a) associated with the data shared by the multiple computer processing threads and

b) divided among a plurality of constraints and each of the plurality of constraints is associated with a different one of the multiple computer processing threads.

15. The computer program product of claim 14 , wherein the computer-readable program code further causes the computer hardware system to perform:

configuring a set of computer software instructions to perform the determining and the using.

16. The computer program product of claim 15 , wherein the computer-readable program code further causes the computer hardware system to perform:

causing each of the multiple computer processing threads to execute a different instance of the computer software instructions.

17. The computer program product of claim 14 , wherein

the data shared by the multiple computer processing threads is a single numeric value.

18. The computer program product of claim 14 , wherein

the data shared by the multiple computer processing threads is a set of multiple elements.

19. The computer program product of claim 14 , wherein

each of the multiple computer processing threads has an associated own thread-local data for storing modifications intended for the data shared by the multiple computer processing thread.

20. The computer program product of claim 14 , wherein the computer-readable program code further causes the computer hardware system to perform:

modifying the data associated with the first computer processing thread with a modification intended for the data shared by the multiple computer processing threads upon a determination that the modification does not violate the constraint.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2021
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: MAPLEBEAR INC.
Reel/Frame 055155/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: YELLIN, DANIEL M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037599/0069 →
Continuity (2)
Continuation 14010591 · Aug 27, 2013
Related Publication 20160139967A1 · May 19, 2016