IP Library Granted Patent US 9,602,055
Granted Patent B1
US 9,602,055 · App. 15/008,183 · Granted Mar 21, 2017

Single-ended mixer with reduced loss

Inventors: Omar Fathy M. Haridy (Cairo, EG); Peter John Katzin (Arlington, MA); Ahmed Adel Hassona (Alexandria, EG)
Assignee: Analog Devices Global
H03D7/1441H01L21/823475H01L23/66H01L2223/6605H01L2223/6688
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Quick Facts
Patent No.
US 9,602,055
App. No.
15/008,183
Granted
Mar 21, 2017
Kind
B1
Abstract

A single-ended mixer having a mismatched, high termination impedance is disclosed. The termination impedance can be mismatched by at least one order of magnitude higher than the standard impedance of a given design environment, such as a 50 Ohm environment for a radio frequency (RF) circuit. The termination impedance can be provided in close physical proximity to the mixer core of the single-ended mixer to allow a suitable bandwidth of operation.

Claims (33)

1. An apparatus comprising:

a mixer core configured to receive a differential input signal and a differential oscillator signal and to generate a differential signal across a first differential node and a second differential node, wherein the second differential node is configured to provide a single-ended output of the mixer core; and

a termination impedance coupled to the first differential node of the mixer core,

wherein the termination impedance is mismatched with a load impedance of a load coupled to the second differential node of the mixer core by at least one order of magnitude at a frequency of the single-ended output.

2. The apparatus of claim 1 , further comprising one or more matching networks at differential oscillator signal nodes of the mixer core.

3. The apparatus of claim 2 , wherein the one or more matching networks are arranged to compensate for mismatch on the first differential node resulting from the termination impedance being mismatched with the load impedance.

4. The apparatus of claim 1 , wherein the termination impedance is physically located approximately as close as possible to the mixer core under layout rules for a process technology used to form the mixer core and the termination impedance.

5. The apparatus of claim 4 , wherein the mixer core and the termination impedance are on a single die.

6. The apparatus of claim 1 , wherein the termination impedance comprises a resistor having a resistance in a range from about 500Ω to 5000 Ω.

7. The apparatus of claim 1 , wherein the second differential node of the mixer core is coupled to a high impedance connection, the high impedance connection having an impedance of at least 0.5 kΩ at a radio frequency.

8. The apparatus of claim 1 , wherein the mixer core comprises a field effect transistor (FET) passive mixer, and wherein a distance between the termination impedance and a first FET of the mixer core is of the same magnitude as a distance between the first FET and a second FET of the mixer core.

9. The apparatus of claim 1 , further comprising an input balun coupled to differential input signal nodes of the mixer core.

10. The apparatus of claim 1 , further comprising a local oscillator balun, wherein the local oscillator balun is coupled to the differential oscillator signal nodes of the mixer core.

11. The apparatus of claim 1 , wherein the load impedance of the second differential node of the mixer core is approximately 50 Ohms.

12. An in-phase/quadrature-phase (I/Q) mixer comprising a plurality of the apparatus of claim 1 .

13. A passive mixer comprising:

a plurality of field effect transistors configured to mix a differential input signal with a differential oscillator signal to generate a differential signal between a first node and a second node, the second node being coupled to a load having a load impedance; and

a high termination impedance electrically coupled to the first node,

wherein the second node is configured to provide a single-ended output of the passive mixer, and

wherein the high termination impedance mismatches the load impedance and is at least 0.5 kΩ at a frequency of the single-ended output.

14. The passive mixer of claim 13 , wherein the termination impedance is approximately as close as possible to the plurality of transistors under layout rules for a process technology used to form the plurality of transistors and the termination impedance.

15. The passive mixer of claim 13 , wherein a distance between the termination impedance and a first field effect transistor of the plurality of field effect transistors is of the same magnitude as a distance between the first field effect transistor and a second field effect transistor of the plurality of field effect transistors.

16. The passive mixer of claim 13 , wherein the passive mixer is a double-balanced field effect transistor (FET) ring mixer.

17. The passive mixer of claim 13 further comprising a matching network at differential nodes across which the differential oscillator signal is received, the matching network being arranged to compensate for mismatch on the first node resulting from the high termination impedance.

18. The passive mixer of claim 13 , wherein the termination impedance is a resistor.

19. The passive mixer of claim 13 , wherein the second node provides a single-ended output of the passive mixer and is coupled to a high impedance connection, the high impedance connection having an impedance of at least 0.5 kΩ at a radio frequency.

20. A method of manufacturing a mixer comprising:

forming a plurality of field effect transistors arranged as a mixer core configured to mix a differential input signal with a differential oscillator signal to generate a differential signal between a first node and a second node;

forming a high termination impedance adjacent to one of the plurality of field effect transistors; and

electrically connecting the high termination impedance to the first node,

wherein the mixer is configured to provide a single-ended output at the second node, the second node being coupled to a load having a load impedance, and

wherein the high termination impedance mismatches the load impedance and is at least one order of magnitude higher than 50Ω at a radio frequency.

21. The method of claim 20 , wherein a distance between the high termination impedance and the one of the plurality of field effect transistors is of the same magnitude as a distance between the one of the plurality of field effect transistors and another of the plurality of field effect transistors.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2022
From: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
To: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
Reel/Frame 059106/0588 →
CHANGE OF NAME Recorded Feb 24, 2022
From: ANALOG DEVICES GLOBAL
To: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
Reel/Frame 059095/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2016
From: HARIDY, OMAR FATHY M.; KATZIN, PETER JOHN; HASSONA, AHMED ADEL
To: ANALOG DEVICES GLOBAL
Reel/Frame 038246/0475 →