Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot

1. A digital phase locked loop (DPLL), comprising:

a time-to-digital converter configured to generate a phase error signal based on a reference clock signal, a current phase signal, and a first phase offset signal, the first phase offset signal being configured to drive the phase error signal toward zero;

a loop filter configured to generate a filtered phase error signal based on the phase error signal and a second phase offset signal, the second phase offset signal being configured to offset the first phase offset signal in the filtered phase error signal; and

a digitally controlled oscillator (DCO) configured to generate an output clock signal of the DPLL based on the filtered phase error signal,

wherein the second phase offset signal is equal to a negative of the first phase offset signal, multiplied by a proportional gain constant of the loop filter.

2. The DPLL of claim 1 , further comprising:

a feedback circuit configured to generate the current phase signal based on the output clock signal of the DPLL.

3. The DPLL of claim 2 , wherein the feedback circuit is further configured to determine a fractional phase difference between the reference clock signal and the output clock signal of the DPLL.

4. The DPLL of claim 1 , wherein the time-to-digital converter is further configured to:

generate an expected phase signal based on the reference clock signal; and

generate the phase error signal as a sum of the first phase offset signal and a difference between the expected phase signal and the current phase signal.

5. The DPLL of claim 1 , further comprising:

a first accumulator circuit configured to integrate a multiple of a phase bump signal to generate the second phase offset signal; and

a second accumulator circuit configured to integrate a negative of the phase bump signal to generate the first phase offset signal.

6. The DPLL of claim 5 , wherein the first accumulator circuit includes an integrator circuit of the loop filter.

7. The DPLL of claim 5 , wherein the second accumulator circuit includes a sampling register of the time-to-digital converter.

8. The DPLL of claim 1 , wherein the loop filter includes:

an output summing node configured to add the second phase offset signal at an output of the loop filter to generate the filtered phase error signal.

9. A method of operating a digital phase locked loop (DPLL), comprising:

generating a phase error signal based on a reference clock signal, a current phase signal, and a first phase offset signal, the first phase offset signal being configured to drive the phase error signal toward zero;

generating a filtered phase error signal based on the phase error signal and a second phase offset signal, the second phase offset signal being configured to offset the first phase offset signal in the filtered phase error signal; and

generating an output clock signal of the DPLL based on the filtered phase error signal,

wherein the second phase offset signal is equal to a negative of the first phase offset signal, multiplied by a proportional gain constant of a loop filter that generates the filtered phase error signal.

10. The method of claim 9 , further comprising:

generating the current phase signal based on the output clock signal of the DPLL.

11. The method of claim 9 , further comprising:

generating an expected phase signal based on the reference clock signal; and

generating the phase error signal as a sum of the first phase offset signal and a difference between the expected phase signal and the current phase signal.

12. The method of claim 9 , further comprising:

integrating a multiple of a phase bump signal to generate the second phase offset signal; and

integrating a negative of the phase bump signal to generate the first phase offset signal.

13. The method claim 9 , further comprising determining a fractional phase difference between the reference clock signal and the output clock signal of the DPLL.

14. The method of claim 9 , wherein generating the filtered phase error signal comprises adding the second phase offset signal at an output of a loop filter to generate the filtered phase error signal.

15. A digital phase locked loop (DPLL), comprising:

a time-to-digital converter configured to generate a phase error signal based on a reference clock signal and a first phase offset signal;

a loop filter configured to generate a filtered phase error signal based on the phase error signal and a second phase offset signal;

a first accumulator circuit configured to receive a phase bump signal and integrate a multiple of the phase bump signal to generate the second phase offset signal; and

a second accumulator circuit configured to receive a negative of the phase bump signal and integrate the negative of the phase bump signal to generate the first phase offset signal.

16. The DPLL of claim 15 , further comprising:

a digitally controlled oscillator (DCO) configured to generate an output clock signal of the DPLL based on the filtered phase error signal.

17. The DPLL of claim 15 , wherein the second phase offset signal is configured to offset the first phase offset signal in the filtered phase error signal.

18. The DPLL of claim 15 , further comprising:

a feedback circuit configured to generate a current phase signal based on the output clock signal of the DPLL.

19. The DPLL of claim 18 , wherein the feedback circuit is further configured to determine a fractional phase difference between the reference clock signal and the output clock signal of the DPLL.

20. The DPLL of claim 18 , wherein the time-to-digital converter is further configured to:

generate an expected phase signal based on the reference clock signal; and

generate the phase error signal as a sum of the first phase offset signal and a difference between the expected phase signal and the current phase signal.

21. The DPLL of claim 15 , wherein the first accumulator circuit includes an integrator circuit of the loop filter.