IP Library Granted Patent US 10,042,648
Granted Patent B2
US 10,042,648 · App. 15/011,948 · Granted Aug 7, 2018

Memory system, electric device, and information processing device

Inventors: Nobuhiro Kondo (Yokohama, JP); Kenichi Maeda (Kamakura, JP); Sven Hegner (Dusseldorf, DE)
Assignee: TOSHIBA MEMORY CORPORATION
G06F9/4401G06F9/45508G06F3/0604G06F3/0632G06F12/0802G06F12/0848G06F12/0868G06F21/79G06F2212/304G06F2212/60
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Quick Facts
Patent No.
US 10,042,648
App. No.
15/011,948
Granted
Aug 7, 2018
Kind
B2
Abstract

A memory system includes a memory and a command generator. The memory is connected to a host including a main memory and a processor connected to the main memory. The command generator generates an initialization command and transmits the initialization command to the host. The initialization command represents a command for instructing the initialization of the main memory and indicating an initialization method for the main memory.

Claims (33)

1. A memory system comprising:

an interface connected to a host including a main memory and a processor to control the main memory; and

a control circuit that generates an initialization command among a plurality of initialization commands and transmits the generated initialization command to the host, the initialization command representing a command for instructing the host to execute initialization of the main memory and indicating an initialization method among a plurality of initialization methods for the main memory, the initialization method corresponding to a pattern of initialization data,

wherein the initialization command generated by the control circuit indicates the initialization method using initialization data including a value obtained by any one of incrementing a predetermined initial pattern, adding a predetermined addition value to a predetermined initial pattern, shifting a value in a predetermined initial pattern, or performing an operation on a predetermined initial pattern by a predetermined algorithm.

2. The memory system according to claim 1 ,

wherein the control circuit receives a response indicating a success or failure of the initialization from the host and interprets the success or failure of the initialization.

3. The memory system according to claim 1 ,

wherein the control circuit generates an initialization command indicating the initialization method using initialization data in which a constant is repeated.

4. The memory system according to claim 1 ,

wherein the control circuit generates an initialization command indicating the initialization method using initialization data in which a predetermined initial pattern is repeated.

5. The memory system according to claim 1 ,

wherein the control circuit generates an initialization command indicating the initialization method using initialization data including a value obtained by repeating a plurality of predetermined repetitive patterns.

6. An electric device comprising:

a main memory; and

a control circuit that receives an initialization command among a plurality of initialization commands from a memory system, interprets the received initialization command, the initialization command representing a command for instructing the host to execute initialization of the main memory and indicating an initialization method among a plurality of initialization methods for the main memory, the initialization method corresponding to a pattern of initialization data, and initializes the main memory by a pattern among a plurality of patterns, indicated by the interpreted initialization command,

the electric device further comprising

an initialization data generator that generates initialization data including a value obtained by any one of incrementing a predetermined initial pattern, adding a predetermined addition value to a predetermined initial pattern, shifting a value in a predetermined initial pattern, or performing an operation on a predetermined initial pattern by a predetermined algorithm, according to the initialization method interpreted by the control circuit.

7. The electric device according to claim 6 ,

wherein the control circuit generates a response indicating a success or failure of the initialization according to the result of the initialization and transmits the generated response.

8. The electric device according to claim 6 :

wherein the initialization data generator generates initialization data in which a constant is repeated, according to the initialization method interpreted by the control circuit.

9. The electric device according to claim 6 :

wherein the initialization data generator generates initialization data in which a predetermined initial pattern is repeated, according to the initialization method interpreted by the control circuit.

10. The electric device according to claim 6 :

wherein the initialization data generator generates initialization data including a value obtained by repeating a plurality of predetermined repetitive patterns, according to the initialization method interpreted by the control circuit.

11. An information processing device comprising:

a memory system including

an interface connected to an electric device, and

a first control circuit that generates an initialization command among a plurality of initialization commands and transmits the generated initialization command to the electric device, the initialization command representing a command instructing the electric device to execute initialization of the main memory and indicating an initialization method among a plurality of initialization methods for the main memory, the initialization method corresponding to a pattern of initialization data, and

the electric device including

a main memory, and

a second control circuit that interprets a received initialization command indicating the initialization method, and initializes the main memory by a pattern among a plurality of patterns indicated by the interpreted initialization command,

wherein the initialization command generated by the first control circuit indicates the initialization method using initialization data including a value obtained by any one of incrementing a predetermined initial pattern, adding a predetermined addition value to a predetermined initial pattern, shifting a value in a predetermined initial pattern, or performing an operation on a predetermined initial pattern by a predetermined algorithm.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043088/0620 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2016
From: KONDO, NOBUHIRO; MAEDA, KENICHI; HEGNER, SVEN
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037632/0242 →
Continuity (2)
Provisional Application 62216801 · Sep 10, 2015
Related Publication 20170075694A1 · Mar 16, 2017