IP Library Granted Patent US 9,565,768
Granted Patent B2
US 9,565,768 · App. 15/013,719 · Granted Feb 7, 2017

Semiconductor package with integrated output inductor on a printed circuit board

Inventor: Eung San Cho (Torrance, CA)
Assignee: Infineon Technologies Americas Corp.
H05K1/185H01L23/5383H01L23/645H05K1/181H05K1/184H01L23/13H01L24/31H05K1/165H05K2201/1003H05K2201/10166
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Quick Facts
Patent No.
US 9,565,768
App. No.
15/013,719
Granted
Feb 7, 2017
Kind
B2
Abstract

A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding 1 around a core, and coupled to the semiconductor die. The winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in the PCB. The control transistor and the sync transistor are configured as a half-bridge. The integrated output inductor is coupled to a switched node of the half-bridge. At least one of the plurality of conductive clips includes a partially etched portion and a non-etched portion. The semiconductor die is attached to the integrated output inductor by a die attach material. The semiconductor die and the integrated output inductor are encapsulated in a molding compound.

Claims (26)

1. A semiconductor package comprising:

a semiconductor die comprising a control transistor and a sync transistor;

an integrated output inductor comprising a winding around a core, and coupled to said semiconductor die;

wherein said winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in said PCB.

2. The semiconductor package of claim 1 wherein said control transistor and said sync transistor are configured as a half-bridge.

3. The semiconductor package of claim 2 wherein said integrated output inductor is coupled to a switched node of said half-bridge.

4. The semiconductor package of claim 1 wherein at least one of said plurality of conductive clips includes a partially etched portion and a non-etched portion.

5. The semiconductor package of claim 1 wherein said semiconductor die further comprises a driver integrated circuit coupled to said control transistor and said sync transistor.

6. The semiconductor package of claim 1 wherein at least one of said control transistor and said sync transistor comprises a group III-V transistor.

7. The semiconductor package of claim 1 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

8. The semiconductor package of claim 1 wherein said core is a ferrite core.

9. The semiconductor package of claim 1 wherein said semiconductor die is situated over and attached to said integrated output inductor by a die attach material.

10. The semiconductor package of claim 1 wherein said semiconductor die and said integrated output inductor are encapsulated in a molding compound.

11. A semiconductor package comprising:

an integrated output inductor comprising a winding around a core;

a power stage stacked over said integrated output inductor, said power stage comprising a control transistor and a sync transistor connected in a half-bridge;

wherein said winding comprises a plurality of conductive clips situated above a printed circuit board (PCB) and connected to a plurality of conductive segments in said PCB.

12. The semiconductor package of claim 11 wherein at least one of said plurality of conductive clips includes a partially etched portion and a non-etched portion.

13. The semiconductor package of claim 11 wherein said integrated output inductor is coupled to a switched node of said half-bridge.

14. The semiconductor package of claim 11 wherein said power stage further comprises a driver integrated circuit coupled to said control transistor and said sync transistor.

15. The semiconductor package of claim 11 wherein said core is a ferrite core.

16. The semiconductor package of claim 11 wherein at least one of said control transistor and said sync transistor comprises a group III-V transistor.

17. The semiconductor package of claim 11 wherein at least one of said control transistor and said sync transistor comprises a group IV transistor.

18. The semiconductor package of claim 11 wherein said control transistor and said sync transistor are monolithically integrated on a semiconductor die.

19. The semiconductor package of claim 18 wherein said semiconductor die is attached to said integrated output inductor by a die attach material.

20. The semiconductor package of claim 11 wherein said power stage and said integrated output inductor are encapsulated in a molding compound.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2016
From: CHO, EUNG SAN
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 037649/0279 →
Continuity (2)
Provisional Application 62137938 · Mar 25, 2015
Related Publication 20160286655A1 · Sep 29, 2016