IP Library Granted Patent US 9,880,770
Granted Patent B2
US 9,880,770 · App. 15/013,855 · Granted Jan 30, 2018

Supporting invalidation commands for non-volatile memory

Inventors: Fan Zhang (Fremont, CA); Taeil Um (San Jose, CA); Yu Cai (San Jose, CA)
Assignee: SK Hynix Inc.
G06F3/064G06F3/0619G06F3/0652G06F3/0679G06F12/0246G06F2212/652G06F2212/7207G06F2212/7209
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Quick Facts
Patent No.
US 9,880,770
App. No.
15/013,855
Granted
Jan 30, 2018
Kind
B2
Abstract

Techniques and systems are provided for tracking commands. Such methods and systems can include maintaining a meta page in a volatile memory to track commands. The meta page can comprise information associated with a non-volatile memory superblock. When an invalidation command is received for a first logical address, the first logical address can be stored along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page.

Claims (39)

1. A method of tracking commands, comprising:

maintaining a meta page in a volatile memory to track commands, wherein the meta page comprises information associated with a non-volatile memory superblock, the superblock comprising a plurality of physical pages;

receiving an invalidation command for a first logical address, the invalidation command indicating that data associated with the first logical address is invalid; and

storing, based on the invalidation command, the first logical address along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page, wherein an index of the first location is usable to determine the physical page corresponding to the first logical address.

2. The method of claim 1 , wherein the determining the physical page corresponding to the first logical address comprises:

determining a number of locations with indices lesser than the index of the first location that have indications that data associated with logical addresses they store is invalid; and

determining a physical address of the physical page corresponding to the first logical address based on the number of locations.

3. The method of claim 1 , wherein the indication that the data associated with the first logical address is invalid includes using an indicator bit of the first location, wherein the indicator bit is a sign bit, and wherein a negative sign implies that that the data associated with the first logical address is invalid.

4. The method of claim 1 , wherein the index of the first location is further usable to determine a position of the invalidation command in a sequence of commands.

5. The method of claim 1 , wherein a plurality of physical pages in the superblock comprise meta data.

6. The method of claim 5 , further comprising indicating in a last physical page of the superblock comprising meta data, locations and a total number of physical pages comprising meta data.

7. The method of claim 5 , further comprising indicating in a physical page comprising meta data, a location of a previous physical page comprising meta data.

8. The method of claim 1 , further comprising:

detecting a triggering of a transfer event; and

transferring contents of the meta page to a non-volatile memory, wherein the transfer event is at least one of: a filled meta page, or a power loss occurrence.

9. The method of claim 8 , further comprising including an end-of-page indicator in the meta page where the transfer event is a power loss occurrence.

10. The method of claim 8 , wherein the transfer event is a closing of the superblock.

11. A non-volatile memory controller, comprising:

one or more processors configured to:

maintain a meta page in a volatile memory to track commands, wherein the meta page comprises information associated with a non-volatile memory superblock, the superblock comprising a plurality of physical pages;

receive an invalidation command for a first logical address, the invalidation command indicating that data associated with the first logical address is invalid; and

store, based on the invalidation command, the first logical address along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page, wherein an index of the first location is usable to determine the physical page corresponding to the first logical address.

12. The non-volatile memory controller of claim 11 , wherein the determining the physical page corresponding to the first logical address comprises:

determining a number of locations with indices lesser than the index of the first location that have indications that data associated with logical addresses they store is invalid; and

determining a physical address of the physical page corresponding to the first logical address based on the number of locations.

13. The controller of claim 11 wherein the indication that the data associated with the first logical address is invalid includes using an indicator bit of the first location, wherein the indicator bit is a sign bit, and wherein a negative sign implies that that the data associated with the first logical address is invalid.

14. The controller of claim 11 , wherein the index of the first location is further usable to determine a position of the invalidation command in a sequence of commands.

15. The controller of claim 11 , wherein a plurality of physical pages in the superblock comprise meta data.

16. The controller of claim 15 , wherein the one or more processors are further configured to indicate in a last physical page of the superblock comprising meta data, locations and a total number of physical pages comprising meta data.

17. The controller of claim 11 , wherein the one or more processors are further configured to indicate in a physical page comprising meta data, a location of a previous physical page comprising meta data.

18. The controller of claim 11 wherein the one or more processors are further configured to:

detect a triggering of a transfer event; and

transfer contents of the meta page to a non-volatile memory, wherein the transfer event is at least one of: a filled meta page, or a power loss occurrence.

19. The controller of claim 18 , wherein the one or more processors are further configured to include an end-of-page indicator in the meta page where the transfer event is a power loss occurrence.

20. The controller of claim 18 , wherein the transfer event is a closing of the superblock.

21. A non-transitory computer readable medium having stored thereon instructions that when executed by a processor perform a method, including:

maintaining a meta page in a volatile memory to track commands, wherein the meta page comprises information associated with a non-volatile memory superblock, the superblock comprising a plurality of physical pages;

receiving an invalidation command for a first logical address, the invalidation command indicating that data associated with the first logical address is invalid; and

storing, based on the invalidation command, the first logical address along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page, wherein an index of the first location is usable to determine the physical page corresponding to the first logical address.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 043389/0705 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2017
From: ZHANG, FAN; UM, TAEIL; CAI, YU
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 043311/0257 →
Continuity (2)
Provisional Application 62213228 · Sep 2, 2015
Related Publication 20170060768A1 · Mar 2, 2017