Electro-optic displays with reduced remnant voltage, and related apparatus and methods
Electro-optic displays with reduced remnant voltage, and related apparatus and methods are provided. A remnant voltage of a pixel of an electro-optic display may be discharged by activating the pixel's transistor and setting the voltages of the front and rear electrodes of the pixel to approximately the same voltage for a specified period of time, and/or until the amount of remnant voltage remaining in the pixel is less than a threshold amount. The remnant voltages of substantially all pixels or a subset of pixels in an active matrix electro-optic display may be simultaneously discharged. The simultaneous discharge of the remnant voltages of pixels may take place when the pixels are in a same state, characterized by (1) the transistor of each pixel being active, and (2) the voltages applied to the front and rear electrodes of each pixel being approximately equal.
1. A method of reducing a remnant voltage of an active matrix electro-optic display having a front electrode and a plurality of pixels, the plurality of pixels each having a rear electrode, where each rear electrode is coupled to a pixel transistor associated with a respective pixel of the plurality of pixels, the method comprising:
applying to the front electrode and to the rear electrodes of the plurality of pixels approximately the same voltage; and
applying to the gate of each of the plurality of pixel transistors a voltage sufficient to activate the plurality of pixel transistors to create a conduction path for draining the remnant voltage, wherein the voltage is applied until a set remnant voltage value is achieved.
2. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is about 300 mV or greater.
3. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is about 450 mV or greater.
4. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is about 700 mV or greater.
5. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is about 1 V or greater.
6. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is about 2 V or greater.
7. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is between about 2 V and about 8 V.
8. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is between about 1 V and about 25 V.
9. The method according to claim 1 , further comprising n-type pixel transistors, wherein the gate voltage to the pixel transistors is equal to or greater than the pixel transistor's activation voltage.
10. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is about −300 mV or less.
11. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is about −450 mV or less.
12. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is about −700 mV or less.
13. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is about −1 V or less.
14. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is about −2 V or less.
15. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is between about −2 V and about −8 V.
16. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is between about −1 V and about −25 V.
17. The method according to claim 1 , further comprising p-type pixel transistors, wherein the gate voltage to the pixel transistors is equal to or less than the pixel transistor's activation voltage.
18. The method according to claim 1 , wherein the voltages are applied for a set duration.
19. The method according to claim 18 , wherein the voltages are applied for about 50 ms to about 300 ms.
20. The method according to claim 18 , wherein the voltages are applied for about 300 ms to about 500 ms.
21. The method according to claim 18 , wherein the voltages are applied for about 500 ms to about 1 sec.
22. The method according to claim 18 , wherein the voltages are applied for about 500 ms to about 3 secs.
23. The method according to claim 18 , wherein the voltages are applied for about 3 secs or longer.
24. The method according to claim 1 , wherein the voltages are applied until the remnant voltage value is equal to or less than 1V.
25. The method according to claim 1 , wherein the voltages are applied until the remnant voltage value is equal to or less than about 500 mV.
26. The method according to claim 1 , wherein the voltages are applied until the remnant voltage value is equal to or less than about 300 mV.
27. The method according to claim 1 , wherein the voltages are applied until the remnant voltage value is equal to or less than about 100 mV.
28. The method according to claim 1 , wherein the voltages are applied until the remnant voltage value is about 0 mV.
29. The method according to claim 1 , wherein substantially all of the pixel transistors are activated concurrently using a driver.
30. The method according to claim 1 , wherein the voltage applied to the front and rear electrodes is greater than or less than 0V.
31. The method according to claim 1 , wherein the electro-optic display is an electrophoretic display.
32. The method according to claim 1 , further comprising:
a floating dwell period, wherein the gate voltage is set to a value to deactivate the pixel transistor for a set duration or until a set remnant voltage value is achieved.
33. A method of reducing remnant voltage of an active matrix electro-optic display having a front electrode and a plurality of pixels each having a rear electrode, where each rear electrode is coupled to a n-type pixel transistor associated with a respective pixel of the plurality of pixels, the method comprising:
grounding the source of each of the n-type pixel transistors;
applying a positive voltage to the gate of each of the n-type pixel transistors to activate the n-type transistors, wherein the voltage is applied until a set remnant voltage value is achieved; and
grounding the front electrode to create a conduction path for draining the remnant voltage.
34. The method according to claim 33 , wherein substantially all of the pixel transistors are activated concurrently using a driver.
35. A method of reducing remnant voltage of an active matrix electro-optic display having a front electrode and a plurality of pixels each having a rear electrode, where each rear electrode is coupled to a p-type pixel transistor associated with a respective pixel of the plurality of pixels, the method comprising:
grounding the source of each of the p-type pixel transistors;
applying a negative voltage to the gate of each of the p-type pixel transistors to activate the p-type transistors, wherein the voltage is applied until a set remnant voltage value is achieved; and
grounding the front electrode to create a conduction path for draining the remnant voltage.
36. The method according to claim 35 , wherein substantially all of the pixel transistors are activated concurrently using a driver.
37. A method of reducing remnant voltage of an active matrix electro-optic display having a front electrode, a plurality of pixels each having a rear electrode, where each rear electrode is coupled to a n-type pixel transistor associated with a respective pixel of the plurality of pixels, the method comprising:
applying to the front electrode a negative voltage;
applying to the source of each of the n-type pixel transistors approximately the same negative voltage as the front electrode; and
grounding the gate of each of the n-type pixel transistors to create a conduction path for draining the remnant voltage.
38. The method according to claim 37 , wherein the electro-optic display is an electrophoretic display.
39. A method of reducing remnant voltage of an active matrix electro-optic display having a front electrode and a plurality of pixels each having a rear electrode, where each rear electrode is coupled to a p-type pixel transistor associated with a respective pixel of the plurality of pixels, the method comprising:
applying to the front electrode a positive voltage;
applying to the source of each of the p-type pixel transistors approximately the same positive voltage as the front electrode; and
grounding the gate of each of the p-type pixel transistors to create a conduction path for draining the remnant voltage.
40. The method according to claim 39 , wherein the electro-optic display is an electrophoretic display.