Devices, systems, and methods for ion trapping
Devices, methods, and systems for ion trapping are described herein. One device includes a through-silicon via (TSV) and a trench capacitor formed around the TSV.
1. A device for ion trapping, comprising:
a through-silicon via (TSV); and
a trench capacitor formed around the TSV, wherein forming the trench capacitor includes:
forming a plurality of annular openings in a substrate;
forming a dielectric material in the openings; and
forming a conductive material on a dielectric material.
2. The device of claim 1 , wherein the device includes a substrate, and wherein the TSV extends through the substrate.
3. The device of claim 1 , wherein the trench capacitor includes a plurality of annular rings, wherein each of the plurality of rings is a different distance from the TSV, and wherein a distance between an annular ring and an adjacent annular ring is between 5 microns and 7 microns.
4. The device of claim 1 , wherein the trench capacitor includes a plurality of annular rings, wherein each of the plurality of rings is a different distance from the TSV, and wherein a distance between an outermost annular ring of the trench capacitor and the TSV is between 5 microns and 200 microns.
5. The device of claim 1 , wherein the trench capacitor includes a plurality of annular rings, wherein each of the plurality of rings is a different distance from the TSV, and wherein at least one of the plurality of annular rings partially encircles the TSV.
6. The device of claim 1 , wherein a height of the trench capacitor is between 55 and 75 microns.
7. The device of claim 1 , wherein a height of the TSV is between 50 and 500 microns.
8. A system for ion trapping, comprising:
a substrate comprising a plurality of devices, each device comprising:
a through-silicon via (TSV); and
a trench capacitor around the TSV, wherein forming the trench capacitor includes:
forming a plurality of annular openings in the substrate;
forming a dielectric material in the openings; and
forming a conductive material on the dielectric material; and
an interposer bonded to the substrate.
9. The system of claim 8 , wherein the interposer is bonded to the substrate via a plurality of gold bond pads.
10. The system of claim 8 , wherein the system includes three planar conductive materials above the substrate.
11. A method of forming a device for ion trapping, comprising:
forming a through-silicon via (TSV) in a substrate; and
forming a trench capacitor around the TSV in the substrate, wherein forming the trench capacitor includes:
forming a plurality of annular openings in the substrate;
forming a dielectric material in the openings; and
forming a conductive material on a dielectric material.
12. The method of claim 11 , wherein the method includes electroplating the TSV.
13. The method of claim 11 , wherein forming the TSV in the substrate includes:
forming a ring-shaped opening in the substrate, the opening defined by a plurality of surfaces of the substrate, wherein the substrate is silicon;
forming a dielectric material on the plurality of surfaces;
forming a conductive material on the dielectric material; and
planarizing a top surface of the substrate and a bottom surface of the substrate;
wherein the conductive material and the dielectric material extend from the top of the substrate to the bottom of the substrate subsequent to planarizing the top surface of the substrate and the bottom surface of the substrate.
14. The method of claim 11 , wherein forming the TSV in the substrate includes:
forming a ring-shaped opening in the substrate, the opening defined by a plurality of surfaces of the substrate, wherein the substrate is silicon;
forming a silicon dioxide material on the plurality of surfaces;
forming a polysilicon material on the silicon dioxide material; and
planarizing a top surface of the substrate and a bottom surface of the substrate.
15. The method of claim 11 , wherein forming the TSV in the substrate includes:
forming a ring-shaped opening in the substrate, the opening defined by a plurality of surfaces of the substrate, wherein the substrate is silicon;
forming a dielectric material on the plurality of surfaces;
forming a first conductive material on the dielectric material;
planarizing a top surface of the substrate and a bottom surface of the substrate;
forming a second conductive material over the first conductive material, the substrate, and the dielectric material;
removing a core portion of the substrate defined by the dielectric material and internal to the dielectric material;
forming a plating base material on the dielectric material; and
forming a third conductive material on the plating base material.
16. The method of claim 15 , wherein the second conductive material is gold.
17. The method of claim 15 , wherein the plating base includes at least one of: tungsten, titanium, and copper.
18. The method of claim 15 , wherein the third conductive material is copper.
19. The method of claim 11 , wherein forming the trench capacitor around the TSV in the substrate includes forming the trench capacitor such that the trench capacitor has a capacitance of approximately 100 picofarads.