Power saving method and apparatus for multimode terminal
View Patent ↗Provided are power saving methods and devices for a multimode terminal. The method includes that: state values CLK 1 _EN/CLK 2 _EN of PWRCTRL 1 /PWRCTRL 2 are controlled and output by using a sleep mode and a wake up mode of a Digital Baseband (DBB) of the multimode terminal; outputs CLK 1 _OUT/CLK 2 _OUT of a radio frequency transceiver (RF TRX) are controlled by using CLK 1 /CLK 2 and the CLK 1 _EN/CLK 2 _EN; and the CLK 1 _OUT/CLK 2 _OUT are sent to a System On chip (SOC)/BUS/Peripheral and a MODEM of the DBB, wherein the CLK 1 _OUT/CLK 2 _OUT serve as a high-speed clock source of the multimode terminal in a standby state and a working state. By the solution, the multimode terminal is enabled to shorten wake up time of the MODEM subsystem and prolong sleep time within a Discontinuous Reception (DRX) period, and the effect of reducing standby power consumption is further achieved.
1. A power saving method for a multimode terminal, the method comprising:
controlling and outputting state values CLK 1 _EN/CLK 2 _EN of PWRCTRL 1 /PWRCTRL 2 by using a sleep mode and a wake up mode of a Digital Baseband (DBB) of the multimode terminal;
controlling outputs CLK 1 _OUT/CLK 2 _OUT of a radio frequency transceiver (RF TRX) by using CLK 1 /CLK 2 and the CLK 1 _EN/CLK 2 _EN; and
sending the CLK 1 _OUT/CLK 2 _OUT to a System On chip (SOC)/BUS/Peripheral and a MODEM of the DBB, wherein the CLK 1 _OUT/CLK 2 _OUT serve as a high-speed clock source of the multimode terminal in a standby state and a working state.
2. The method as claimed in claim 1 , wherein the DBB has a Weak Pull High Function.
3. The method as claimed in claim 2 , before controlling the output CLK 1 _OUT/CLK 2 _OUT of the RF TRX by using the CLK 1 /CLK 2 and the CLK 1 _EN/CLK 2 _EN, further comprising:
controlling a Power Management Integrated Circuit (PMIC) to turn on/off output power suppliers VCLK 1 _EN/VCLK 2 _EN; and
controlling, in a manner of controlling the VCLK 1 _EN/VCLK 2 _EN, whether VCTCXO or CRYSTAL outputs a clock or not.
4. The method as claimed in claim 3 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
5. The method as claimed in claim 2 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
6. The method as claimed in claim 1 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
7. A power saving device for a multimode terminal, wherein the power saving device is located in the multimode terminal and comprises:
a first control component, configured to control and output state values CLK 1 _EN/CLK 2 _EN of PWRCTRL 1 /PWRCTRL 2 by using a sleep mode and a wake up mode of a Digital Baseband (DBB) of the multimode terminal;
a second control component, configured to control outputs CLK 1 _OUT/CLK 2 _OUT of a radio frequency transceiver (RF TRX) by using CLK 1 /CLK 2 and the CLK 1 _EN/CLK 2 _EN; and
a sending component, configured to send the CLK 1 _OUT/CLK 2 _OUT to a System On chip (SOC)/BUS/Peripheral and a MODEM of the DBB, wherein the CLK 1 _OUT/CLK 2 _OUT serve as a high-speed clock source of the multimode terminal in a standby state and a working state.
8. The device as claimed in claim 7 , wherein the DBB has a Weak Pull High Function.
9. The device as claimed in claim 8 , further comprising:
a third control component, coupled to the second control component and configured to control a Power Management Integrated Circuit (PMIC) to turn on/off output power suppliers VCLK 1 _EN/VCLK 2 _EN; and
a fourth control component, coupled to the third control component and configured to control, in a manner of controlling the VCLK 1 _EN/VCLK 2 _EN, whether VCTCXO or CRYSTAL outputs a clock or not.
10. The device as claimed in claim 9 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
11. The device as claimed in claim 8 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
12. The device as claimed in claim 7 , wherein an operation mode of the multimode terminal comprises one of the following combinations:
4th-Generation/3rd-Generation (4G/3G) serving as one standby/one active and 2nd-Generation (2G) serving as the other standby/the other active; and
4G serving as one standby/one active and 3G/2G serving as the other standby/the other active.
13. A power saving method for a multimode terminal, wherein the method is applied to a multimode terminal adopting a 4th-Generation/3rd-Generation (4G/3G) and 2nd-Generation (2G) operation mode and comprises:
controlling and outputting state values CLK 1 _EN/CLK 2 _EN of PWRCTRL 1 /PWRCTRL 2 by using a sleep mode and a wake up mode of a Digital Baseband (DBB) of the multimode terminal;
controlling output power suppliers V_3G/4G and V_2G of a Power Management Integrated Circuit (PMIC) according to the CLK 1 _EN/CLK 2 _EN; and
providing the V_3G/4G and V_2G to a radio frequency transceiver (RF TRX) and an RF Front-End Module (FEM) of each MODEM subsystem.
14. A power saving device for a multimode terminal, wherein the device is located in a multimode terminal adopting a 4th-Generation/3rd-Generation (4G/3G) and 2nd-Generation (2G) operation mode and comprises:
a first control component, configured to control and output state values CLK 1 _EN/CLK 2 _EN of PWRCTRL 1 /PWRCTRL 2 by using a sleep mode and a wake up mode of a Digital Baseband (DBB) of the multimode terminal;
a second control component, configured to control output power suppliers V_3G/4G and V_2G of a Power Management Integrated Circuit (PMIC) according to the CLK 1 _EN/CLK 2 _EN; and
a provision component, configured to provide the V_3G/4G and V_2G to a radio frequency transceiver (RF TRX) and an RF Front-End Module (FEM) of each MODEM subsystem.