IP Library Granted Patent US 9,898,406
Granted Patent B2
US 9,898,406 · App. 15/040,030 · Granted Feb 20, 2018

Caching of data in data storage systems by managing the size of read and write cache based on a measurement of cache reliability

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,898,406
App. No.
15/040,030
Granted
Feb 20, 2018
Kind
B2
Abstract

A disk drive is disclosed that varies its caching policy for caching data in non-volatile solid-state memory as the memory degrades. As the non-volatile memory degrades, the caching policy can be varied such that the non-volatile memory is used more as a read cache and less as a write cache. Performance improvements and slower degradation of the non-volatile memory can thereby be attained.

Claims (49)

1. In a data storage system comprising a non-volatile memory and a controller, a method of caching data in the non-volatile memory, the method comprising:

from a plurality of logical address ranges, identifying a first subset of logical address ranges that are frequently accessed by a host relative to a first threshold;

identifying a second subset of logical address ranges from the first subset of logical address ranges, each logical address range in the second subset being frequently written by the host relative to a second threshold;

determining a reliability measurement of the non-volatile memory; and

for each logical address range in the first subset of logical address ranges:

determining a metric corresponding to a frequency of access of the logical address range by the host, the metric associated with a number of read and write commands directed by the host to the logical address range;

determining that the logical address range is included in the second subset;

in response to determining that the logical address range is included in the second subset:

adjusting the metric to account for a frequency of the host writing to the logical address range and the reliability measurement,

determining that the metric exceeds a caching threshold, and

in response to determining that the metric exceeds the caching threshold, writing data associated with the logical address range to the non-volatile memory, and

in response to determining that the logical address range is not included in the second subset, writing data associated with the logical address range to the non-volatile memory provided that the metric associated with the logical address range exceeds the caching threshold,

wherein when the reliability measurement falls below a minimum reliability threshold so that frequently written data from the second subset of logical address ranges is not written to the non-volatile memory, at least some frequently accessed data from the first subset of logical address ranges is written to the non-volatile memory, and

wherein the method is performed by the controller.

2. The method of claim 1 , wherein identifying the first subset of logical address ranges comprises determining that a number of read and write commands issued by the host to a logical address range exceeds an access threshold.

3. The method of claim 2 , wherein identifying the second subset of logical address ranges comprises determining that a number of write commands issued by the host to a logical address range exceeds a write threshold.

4. The method of claim 1 , wherein the reliability measurement corresponds at least in part to a remaining usable life of the non-volatile memory.

5. The method of claim 4 , wherein the remaining usable life corresponds at least in part to a number of remaining program-erase cycles of the non-volatile memory.

6. The method of claim 1 , wherein adjusting the metric comprises:

in response to determining that the frequency of the host writing to the logical address range exceeds a write frequency threshold, decreasing the metric based on the reliability measurement.

7. The method of claim 6 , further comprising decreasing the metric in response to determining that the reliability measurement is below a reliability threshold.

8. The method of claim 6 , further comprising decreasing the metric according to one or more of a linear, piecewise linear, or non-linear relationships between the reliability measurement and a portion of the non-volatile memory allocated to storing frequently written data.

9. The method of claim 6 , further comprising decreasing the metric according to a characterization of data stored in the non-volatile memory.

10. The method of claim 1 , wherein non-volatile memory comprises solid-state memory.

11. A data storage system for storing data received from a host, comprising:

a non-volatile memory; and

a controller configured to communicate with at least the non-volatile memory in response to receiving read and write commands from the host, the controller further configured to:

identify from a plurality of logical address ranges, a first subset of logical address ranges that are frequently accessed by the host relative to a first threshold;

identify a second subset of logical address ranges from the first subset of logical address ranges, each logical address range in the second subset being frequently written by the host relative to a second threshold;

determine a reliability measurement of the non-volatile memory;

for each logical address range in the first subset of logical address ranges, determine a metric corresponding to a frequency of access of the logical address range by the host, the metric associated with a number of read and write commands directed by the host to the logical address range;

in response to a determination that the logical address range is included in the second subset:

adjust the metric to account for a frequency of the host writing to the logical address range and the reliability measurement, and

in response to a determination that the metric exceeds a caching threshold, write data associated with the logical address range to the non-volatile memory; and

in response to a determination that the logical address range is not included in the second subset, write data associated with the logical address range to the non-volatile memory when the metric associated with the logical address range exceeds the caching threshold,

wherein when the reliability measurement falls below a minimum reliability threshold so that frequently written data from the second subset of logical address ranges is not written to the non-volatile memory, at least some frequently accessed data from the first subset of logical address ranges is written to the non-volatile memory.

12. The system of claim 11 , wherein the controller is configured to identify the first subset of logical address ranges based on at least determining that a number of read and write commands issued by the host to a logical address range exceeds an access threshold.

13. The system of claim 12 , wherein the controller is configured to identify the second subset of logical address ranges based on at least determining that a number of write commands issued by the host to a logical address range exceeds a write threshold.

14. The system of claim 11 , wherein the reliability measurement corresponds at least in part to a remaining usable life of the non-volatile memory.

15. The system of claim 14 , wherein the remaining usable life corresponds at least in part to a number of remaining program-erase cycles of the non-volatile memory.

16. The system of claim 11 , wherein the controller is configured to adjust the metric by decreasing the metric based on the reliability measurement in response to determining that the frequency of the host writing to the logical address range exceeds a write frequency threshold.

17. The system of claim 16 , wherein controller is further configured to decrease the metric in response to a determination that the reliability measurement is below a reliability threshold.

18. The system of claim 16 , wherein the controller is further configured to decrease the metric according to one or more of a linear, piecewise linear, or non-linear relationships between the reliability measurement and a portion of the non-volatile memory allocated to storing frequently written data.

19. The system of claim 16 , wherein the controller is further configured to decrease the metric according to a characterization of data stored in the non-volatile memory.

20. The system of claim 11 , wherein non-volatile memory comprises solid-state memory.

21. The method of claim 1 , further comprising increasing the caching threshold in response to determining that the reliability measurement is below a reliability threshold.

22. The system of claim 11 , wherein the controller is further configured to increase the caching threshold in response to a determination that the reliability measurement is below a reliability threshold.

23. The method of claim 8 , further comprising decreasing the metric according to a linear and non-linear relationship between the reliability measurement and a portion of the non-volatile memory allocated to storing frequently written data.

24. The system of claim 18 , wherein the controller is further configured to decrease the metric according to a linear and non-linear relationship between the reliability measurement and a portion of the non-volatile memory allocated to storing frequently written data.

Assignments (6)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 039389 FRAME 0699 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0553 →
RELEASE OF SECURITY INTEREST Recorded Aug 16, 2016
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 039444/0802 →
SECURITY AGREEMENT Recorded Jul 19, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039389/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2016
From: HORN, ROBERT L.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 037977/0917 →