IP Library Granted Patent US 10,031,670
Granted Patent B2
US 10,031,670 · App. 15/040,431 · Granted Jul 24, 2018

Control unit and control method for controlling writes and background operations of multiple semiconductor storage devices

Inventor: Akihiro Toge (Yokohama, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0605G06F3/064G06F3/0611G06F3/0656G06F3/0659G06F3/0679G06F11/1068G06F12/0253G11C16/10G11C16/26G06F12/0261G06F12/0269G06F12/0276G11C29/52
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Quick Facts
Patent No.
US 10,031,670
App. No.
15/040,431
Granted
Jul 24, 2018
Kind
B2
Abstract

According to one embodiment, a control unit writes data in a write buffer to a first semiconductor storage device, and requests the first semiconductor storage device to start a background operation. The control unit writes the data to a second semiconductor storage device, and requests the second semiconductor storage device to start a background operation. When the first semiconductor device is in a busy state because of the write operation or the background operation, the control unit reads data from either the second semiconductor storage device or the write buffer.

Claims (47)

1. A control unit connectable to first to third semiconductor storage devices which include respective nonvolatile memories, the control unit comprising:

a write buffer configured to temporarily store data blocks to be written, which are received from a host; and

a controller configured to:

write, to the first semiconductor storage device, a first data block included in the data blocks;

request the first semiconductor storage device to start a background operation, after receiving a response indicating write completion from the first semiconductor storage device;

write, to the second semiconductor storage device, a second data block included in the data blocks, after the first semiconductor storage device completes the background operation;

request the second semiconductor storage device to start a background operation, after receiving a response indicating write completion from the second semiconductor storage device;

write, to the third semiconductor storage device, a redundancy code calculated from the first and second data blocks, after the first semiconductor storage device completes the background operation;

request the third semiconductor storage device to start a background operation, after receiving a response indicating write completion from the third semiconductor storage device;

read the second data block from the second semiconductor storage device, read the redundancy code from the third semiconductor storage device, and generate the first data block using the read second data block and the read redundancy code, when data designated by a read command received from the host is included in the first data block, and the first semiconductor storage device is in a busy state due to the write operation or the background operation; and

transmit the generated first data block to the host,

wherein the first data block, the second data block and the redundancy code form one stripe.

2. The control unit of claim 1 , wherein the controller is further configured to switch a semiconductor storage device, to which the redundancy code is to be written, among the first semiconductor storage device, the second semiconductor storage device, and the third semiconductor storage device.

3. The control unit of claim 1 , wherein

a period in which the second semiconductor device is in a busy state because of the write operation or the background operation does not overlap a period in which the first semiconductor device is in the busy state because of the write operation or the background operation; and

a period in which the third semiconductor device is in a busy state because of the write operation or the background operation does not overlap the period in which the second semiconductor device is in the busy state because of the write operation or the background operation.

4. The control unit of claim 1 , wherein during a period in which the first semiconductor device is in the busy state because of the write operation or the background operation, the controller sets the second and third semiconductor storage devices in a standby state in which the second and third semiconductor storage devices are prepared to respond to the read command.

5. The control unit of claim 1 , wherein the background operation includes a garbage collection operation.

6. The control unit of claim 1 , wherein when start of the background operation is requested, each of the first, second and third semiconductor storage devices performs a garbage collection operation.

7. The control unit of claim 6 , wherein

when the start of the background operation is requested, each of the first, second and third semiconductor storage devices determines whether the number of free blocks is not less than a threshold;

when the number of the free blocks is not less than the threshold, each of the first, second and third semiconductor storage devices transmits, to the control unit, a response indicating completion of the background operation, without performing the garbage collection operation; and

when the number of the free blocks is less than the threshold, each of the first, second and third semiconductor storage devices performs the garbage collection operation.

8. The control unit of claim 1 , wherein

the first, second and third semiconductor storage devices further include respective device controllers;

a respective one of the device controllers is configured to:

control a corresponding one of the nonvolatile memories;

determine whether the number of free blocks included in the corresponding one of the nonvolatile memories is not less than a threshold, when start of the background operation is requested; and

transmit, to the control unit, a response indicating completion of the background operation, without performing a garbage collection operation on the corresponding one of the nonvolatile memories, when the number of the free blocks included in the corresponding one of the nonvolatile memories is not less than the threshold.

9. A method of controlling first to third semiconductor storage devices which include respective nonvolatile memories, the method comprising:

temporarily storing, in a write buffer, data blocks to be written, which are received from a host;

writing, to the first semiconductor storage device, a first data block included in the data blocks;

requesting the first semiconductor storage device to start a background operation, after receiving a response indicating write completion from the first semiconductor storage device;

writing, to the second semiconductor storage device, a second data block included in the data blocks, after the first semiconductor storage device completes the background operation;

requesting the second semiconductor storage device to start a background operation, after receiving a response indicating write completion from the second semiconductor storage device;

writing, to the third semiconductor storage device, a redundancy code calculated from the first and second data blocks, after the second semiconductor storage device completes the background operation;

requesting the third semiconductor storage device to start a background operation, after receiving a response indicating write completion from the third semiconductor storage device, the first and second data blocks and the redundancy code forming one stripe; and

reading the second data block from the second semiconductor storage device, reading the redundancy code from the third semiconductor storage device, generating the first data block using the read second data block and the read redundancy code, and transmitting the generated first data block to the host, when data designated by a read command from the host is included in the first data block, and the first semiconductor device is in a busy state because of the write operation or the background operation.

10. The method of claim 9 , wherein

a period in which the second semiconductor device is in a busy state because of the write operation or the background operation does not overlap a period in which the first semiconductor device is in the busy state because of the write operation or the background operation; and

a period in which the third semiconductor device is in a busy state because of the write operation or the background operation does not overlap the period in which the second semiconductor device is in the busy state because of the write operation or the background operation.

11. The method of claim 9 , wherein the background operation includes a garbage collection operation.

12. The method of claim 9 , wherein when start of the background operation is requested, each of the first, second and third semiconductor storage devices performs a garbage collection operation.

13. The method of claim 12 , wherein

when the start of the background operation is requested, each of the first, second and third semiconductor storage devices determines whether the number of free blocks is not less than a threshold;

when the number of the free blocks is not less than the threshold, each of the first, second and third semiconductor storage devices transmits a response indicating completion of the background operation, without performing the garbage collection operation; and

when the number of the free blocks is less than the threshold, each of the first, second and third semiconductor storage devices performs the garbage collection operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0798 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: TOGE, AKIHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037702/0208 →
Continuity (2)
Provisional Application 62214473 · Sep 4, 2015
Related Publication 20170068456A1 · Mar 9, 2017