Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.
1. A non-volatile memory cell, comprising:
a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel;
an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel;
the drains of the p-channel non-volatile transistor and the n-channel non-volatile transistor connected together to a control line;
a lightly-doped drain region extending from the drain of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor, and a lightly-doped drain region extending from the source of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor, the lightly-doped drain region extending from the source of the p-channel non-volatile transistor being shorter than the lightly-doped drain region extending from the drain of the p-channel non-volatile transistor.
2. The non-volatile memory cell of claim 1 further including a volatile switch transistor having a gate connected to the control line.
3. The non-volatile memory cell of claim 1 further comprising:
a high column line connected to the source of the p-channel non-volatile transistor; and
a low column line connected to the source of the n-channel non-volatile transistor.
4. The non-volatile memory cell of claim 1 wherein:
the source and drain regions of the p-channel non-volatile transistor are doped with boron or BF 2 to a concentration of between about 1E18 atoms/cm 3 and about 1E20 atoms/cm 3 ; and
the source and drain regions of the n-channel non-volatile transistor are doped with arsenic or phosphorus to a concentration of between about 1E18 atoms/cm 3 and about 1E20atoms/cm 3 .
5. The non-volatile memory cell of claim 4 wherein
the lightly-doped drain regions of the p-channel non-volatile transistor are doped with boron to a concentration of between about 1E16 atoms/cm 3 and about 1E18 atoms/cm 3 ; and
the lightly-doped drain regions of the p-channel non-volatile transistor are doped with arsenic or phosphorus to a concentration of between about 1E16 atoms/cm 3 and about 1E18atoms/cm 3 .
6. The non-volatile memory cell of claim 1 wherein:
the lightly doped drain region on the drain side of the p-channel nonvolatile transistor extends past the channel-side of the drain region of the p-channel nonvolatile transistor by between about 0.2 μm and about 1.0 μm;
the lightly doped drain region on the source side of the p-channel nonvolatile transistor extends past the channel-side of the source region of the p-channel nonvolatile transistor by between about 0.01 μm and about 0.1 μm;
the lightly doped drain region on the drain side of the n-channel nonvolatile transistor extends past the channel-side of the drain region of the p-channel nonvolatile transistor by between about 0.2 μm and about 1.0 μm; and
the lightly doped drain region on the source side of the n-channel nonvolatile transistor extends past the channel-side of the source region of the p-channel nonvolatile transistor by between about 0.01 μm and about 0.1 μm.