NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME

1 . A non-volatile memory cell, comprising:

a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel;

an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel;

the drains of the p-channel non-volatile transistor connected together to a control line;

in at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extending only from the drain towards the channel.

2 . The non-volatile memory cell of claim 1 further including a volatile switch transistor having a gate connected to the control line.

3 . The non-volatile memory cell of claim 1 wherein the lightly-doped drain region extends only from the drain of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor.

4 . The non-volatile memory cell of claim 3 further comprising a lightly-doped drain region extending from the source of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor.

5 - 6 . (canceled)

7 . The non-volatile memory cell of claim 1 wherein the lightly-doped drain region extends from the drain of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor.

8 . The non-volatile memory cell of claim 7 further comprising a lightly-doped drain region extending from the source of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor.

9 - 10 . (canceled)

11 . The non-volatile memory cell of claim 1 wherein:

a lightly-doped drain region extends from the drain of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor; and

a lightly-doped drain region extends from the drain of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor.

12 . The non-volatile memory cell of claim 1 further including a volatile switch transistor having a gate connected to the control line.

13 . The non-volatile memory cell of claim 11 further comprising:

a lightly-doped drain region extending from the source of the p-channel non-volatile transistor towards the channel of the p-channel non-volatile transistor; and

a lightly-doped drain region extending from the source of the n-channel non-volatile transistor towards the channel of the n-channel non-volatile transistor.

14 - 15 . (canceled)

16 . A method for fabricating non-volatile memory cell on a semiconductor substrate comprising:

defining active device areas in the semiconductor substrate;

forming shallow trench isolation regions in the semiconductor substrate;

implanting a p-well region for an n-channel memory transistor and an n-well region for a p-channel memory transistor in the semiconductor substrate;

forming gate oxide regions for an n-channel memory transistor and an n-well region for a p-channel memory transistor;

forming first and second polysilicon layers with an intervening inter-poly dielectric layer;

forming a polysilicon gate stack for each of the n-channel and p-channel memory transistors from the first and second polysilicon layers;

forming lightly doped drain regions at only a drain side of the gate of the p-channel memory transistor;

forming spacers at the edge of the gate of the p-channel memory transistor;

performing and annealing source and drain implants for both the p-channel and the n-channel memory transistors; and

performing metallization and passivation processes, are performed to complete the integrated circuit device.

17 . The method of claim 16 , further comprising:

forming lightly doped drain regions at a drain side of the gate of the n-channel memory transistor; and

forming spacers at the edge of the gate of the n-channel memory transistor.