IP Library Granted Patent US 10,217,740
Granted Patent B2
US 10,217,740 · App. 15/041,535 · Granted Feb 26, 2019

Semiconductor device and radio frequency module formed on high resistivity substrate

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Quick Facts
Patent No.
US 10,217,740
App. No.
15/041,535
Granted
Feb 26, 2019
Kind
B2
Abstract

A semiconductor device includes a high resistivity substrate, a first deep well region having a first conductive type and formed in the high resistivity substrate, a second deep well region having a second conductive type and formed on the first deep well region, a first well region having the first conductive type and formed on the second deep well region, and a transistor formed on the first well region.

Claims (54)

1. A semiconductor device comprising:

a high resistivity substrate;

a first deep well region having a first conductive type and arranged within the high resistivity substrate;

a second deep well region having a second conductive type and arranged on the first deep well region;

a first well region having the first conductive type and arranged on the second deep well region;

a transistor arranged on the first well region;

a device isolation region arranged in the high resistivity substrate to surround the first well region and comprising a deep trench device isolation region;

a second well region having the second conductive type and arranged outside the device isolation region; and

a third well region having the first conductive type and arranged outside the second well region,

wherein the second deep well region is arranged wider than the first well region,

the first deep well region is arranged wider than the second deep well region, and

the device isolation region extends through the second deep well region and the first deep well region so as to be deeper than the first deep well region and has a slit to electrically connect the second deep well region with the second well region and the first deep well region with the third well region.

2. The semiconductor device of claim 1 , wherein the transistor comprises:

a gate structure arranged on the first well region;

source and drain regions arranged at surface portions of the first well region adjacent to opposite sides of the gate structure; and

a high concentration impurity region arranged on one side of the source region.

3. The semiconductor device of claim 2 , wherein the source region has the second conductive type;

the high concentration impurity region has the first conductive type; and

the source region and the high concentration impurity region are electrically connected with each other.

4. The semiconductor device of claim 1 , wherein the device isolation region further comprises a shallow trench device isolation region arranged on the deep trench device isolation region.

5. The semiconductor device of claim 1 , wherein a second high concentration impurity region having the second conductive type is arranged on the second well region.

6. The semiconductor device of claim 5 , wherein a third high concentration impurity region having the first conductive type is arranged on the third well region.

7. A semiconductor device comprising:

a high resistivity substrate having a first conductive type;

a first deep well region having the first conductive type and arranged in the high resistivity substrate;

a second deep well region having a second conductive type and arranged on the first deep well region;

a first well region having the first conductive type and arranged on the second deep well region;

a plurality of transistors arranged on the first well region and connected with one another to have a multi-finger structure;

a device isolation region arranged in the high resistivity substrate to surround the first well region and comprising a deep trench device isolation region;

a second well region having the second conductive type and arranged outside the device isolation region; and

a third well region having the first conductive type and arranged outside the second well region,

wherein the second deep well region is arranged wider than the first well region,

the first deep well region is arranged wider than the second deep well region, and

the device isolation region extends through the second deep well region and the first deep well region so as to be deeper than the first deep well region and has a slit to electrically connect the second deep well region with the second well region and the first deep well region with the third well region.

8. The semiconductor device of claim 7 , wherein a high concentration impurity region having the first conductive type is arranged between source regions of transistors disposed adjacent with each other among the plurality of transistors; and

the high concentration impurity region and the source regions of the adjacent transistors are electrically connected with one another.

9. The semiconductor device of claim 7 , wherein the device isolation region further comprises a shallow trench device isolation region arranged on the deep trench device isolation region.

10. The semiconductor device of claim 9 , wherein a second high concentration impurity region having the second conductive type is arranged on the second well region.

11. A radio frequency (RF) module comprising:

an RF switching device arranged on a high resistivity substrate;

an RF active device arranged on the high resistivity substrate;

an RF passive device arranged on the high resistivity substrate; and

a control device arranged on the high resistivity substrate,

wherein at least one of the RF active device and the control device comprises:

a first deep well region having a first conductive type and arranged in the high resistivity substrate;

a second deep well region having a second conductive type and arranged on the first deep well region;

a first well region having the first conductive type and arranged on the second deep well region;

a transistor arranged on the first well region;

a device isolation region arranged in the high resistivity substrate to surround the first well region and comprising a deep trench device isolation region;

a second well region having the second conductive type and arranged outside the device isolation region; and

a third well region having the first conductive type and arranged outside the second well region,

wherein the second deep well region is arranged wider than the first well region,

the first deep well region is arranged wider than the second deep well region, and

the device isolation region extends through the second deep well region and the first deep well region so as to be deeper than the first deep well region and has a slit to electrically connect the second deep well region with the second well region and the first deep well region with the third well region.

Assignments (2)
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD.
Reel/Frame 044559/0819 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2016
From: CHO, YONG SOO
To: DONGBU HITEK CO., LTD.
Reel/Frame 037772/0732 →