IP Library Granted Patent US 9,785,881
Granted Patent B2
US 9,785,881 · App. 15/043,885 · Granted Oct 10, 2017

System and method for producing an electronic device

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Quick Facts
Patent No.
US 9,785,881
App. No.
15/043,885
Granted
Oct 10, 2017
Kind
B2
Abstract

A method and system for producing electronic label are disclosed. The electronic label includes a first substrate and a second substrate. Layout information associated with the electronic label is developed. The layout information is automatically processed to develop print commands, circuit layout information, and component placement information therefrom. Information is printed on the first substrate in accordance with the print information and a conductive trace is deposited on the second substrate in accordance with circuit layout information. Components are placed on the deposited conductive trace in accordance with the component placement information.

Claims (28)

1. A method for producing an electronic device that includes a substrate, the method comprising the steps of:

providing a graphical user interface to develop layout information associated with the electronic device, wherein the layout information specifies a condition that the electronic device is adapted to sense, a location on the substrate of an indicator, and a characteristic of the indicator;

processing the layout information to automatically select a processor, a first component adapted to sense the condition, and a second component in accordance with the characteristic of the indicator and to automatically develop from the layout information circuit trace information and component placement information, wherein the component placement information includes placement information of the first component, the second component and the processor, and specification of interconnects between the processor and the first and second components;

depositing on the substrate at least one conductive trace in accordance with the circuit trace information; and

placing the first and second components and the processor on the at least one deposited conductive trace in accordance with the component placement information.

2. The method of claim 1 , wherein the step of processing the layout information comprises the step of generating a netlist, wherein the netlist identifies components that comprise the electronic device and the interconnections therebetween.

3. The method of claim 2 , wherein the step of processing the layout information comprises supplying the netlist to an automated circuit layout program, and receiving circuit trace information from the circuit layout program.

4. The method of claim 1 , wherein the substrate comprises a first substrate and the electronic device includes a second substrate, and processing the layout information includes developing from the layout commands print commands associated with print information, further including the step of printing on at least one of the first substrate and the second substrate in accordance with the print commands.

5. The method of claim 4 , wherein the step of processing the layout information comprises combining the circuit trace information with the print commands into a single file.

6. The method of claim 1 , wherein the layout information includes information regarding a location on the second and behavior of a sensor.

7. The method of claim 6 , wherein the layout information includes information regarding an action undertaken by the electronic device in response to actuation of the sensor.

8. The method of claim 1 , wherein the indicator is one of a visual indicator, an auditory indicator, or a vibration motor.

9. The method of claim 1 , comprising the further step of finishing the substrate to produce a finished electronic device, wherein finishing the substrate comprises one or more of joining the first substrate with another substrate, die-cutting the substrate, die-cutting the joined substrates, and creating an aperture in the substrate.

10. The method of claim 1 , wherein processing the layout instructions includes the step of generating from the layout information executable instructions to download to the electronic device, and the method comprises the further step of downloading the executable instructions into a memory of the electronic device.

11. A system for producing an electronic device that includes a substrate, comprising:

a composition system that includes a graphical user interface to develop layout information associated with the electronic device, wherein the layout information specifies a condition that the electronic device is adapted to sense, a location on the substrate of an indicator, and a characteristic of the indicator;

a circuit layout generator that processes the layout information to automatically select a processor, a first component adapted to sense the condition, and a second component in accordance with the characteristic of the indicator and to automatically develop from the layout information circuit trace information and component placement information, wherein the component placement information includes placement information of the first component, the second component and the processor, and specification of interconnects between the processor and the first and second components;

a printing system that deposits on the substrate at least one conductive trace in accordance with the circuit trace information; and

a component placement system that places the first and second components and the processor on the at least one deposited conductive trace in accordance with the component placement information.

12. The system of claim 11 , wherein the circuit layout generator creates a netlist, wherein the netlist identifies components that comprise the electronic device and the interconnections therebetween.

13. The system of claim 12 , further including an automated circuit layout program that generates circuit trace information.

14. The system of claim 11 , wherein the substrate includes a first substrate and the electronic device includes a second substrate, further including a print command generator that processes the layout information to automatically develop therefrom print commands, and the printing system prints on at least one of the first substrate and the second substrate information in accordance with the print commands.

15. The system of claim 14 , wherein the print command generator combines the circuit trace information with the print commands into a single file.

16. The system of claim 11 , wherein the layout information includes information regarding a location on the substrate and behavior or a sensor.

17. The system of claim 11 , wherein the layout information includes information regarding an action undertaken by the electronic device in response to actuation of the sensor.

18. The system of claim 11 , wherein the indicator is one of a visual indicator, an auditory indicator, or a vibration motor.

19. The system of claim 11 , further including a finishing system to produce a finished electronic device, wherein the finishing system undertakes one or more of joining the substrate with another substrate, die-cutting the substrate, die-cutting the joined substrates, and creating an aperture in the substrate.

20. The system of claim 11 , further including a program generator that generates from the layout information executable instructions to download to the electronic device, and a programming system that downloads the executable instructions into a memory of the electronic device.

Assignments (19)
INTELLECTUAL PROPERTY ASSIGNMENT AGREEMENT Recorded Apr 22, 2025
From: WELLS FARGO BANK, NATIONAL ASSOCIATION
To: BANK OF AMERICA, N.A.
Reel/Frame 070919/0394 →
PATENT SECURITY AGREEMENT Recorded Aug 9, 2024
From: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.; VALASSIS COMMUNICATIONS, INC.; VALASSIS DIGITAL CORP.; VALASSIS DIRECT MAIL, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 068534/0447 →
PATENT SECURITY AGREEMENT Recorded Aug 9, 2024
From: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.; VALASSIS COMMUNICATIONS, INC.; VALASSIS DIGITAL CORP.; VALASSIS DIRECT MAIL, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
Reel/Frame 068534/0366 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (R/F 064463/0597) Recorded Aug 9, 2024
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
To: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
Reel/Frame 068534/0330 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (R/F 064462/0445) Recorded Aug 9, 2024
From: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION
To: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
Reel/Frame 068534/0306 →
PATENT SECURITY AGREEMENT Recorded Aug 9, 2024
From: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.; VALASSIS DIGITAL CORP.; VALASSIS DIRECT MAIL, INC.; VALASSIS COMMUNICATIONS, INC.
To: APOLLO ADMINISTRATIVE AGENCY LLC
Reel/Frame 068533/0812 →
RELEASE OF SECURITY INTEREST Recorded Jul 22, 2024
From: APOLLO ADMINISTRATIVE AGENCY LLC, AS ADMINISTRATIVE AGENT
To: R.R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
Reel/Frame 068467/0314 →
RELEASE OF SECURITY INTEREST RECORDED AT RF 056122/0839; ASSIGNED VIA RF 059203/0333 TO JEFFERIES AND RF 063487/0449 TO APOLLO Recorded Apr 17, 2024
From: APOLLO ADMINISTRATIVE AGENCY LLC
To: R.R. DONNELLEY & SONS COMPANY
Reel/Frame 067131/0845 →
SECURITY INTEREST Recorded Apr 3, 2024
From: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
To: APOLLO ADMINISTRATIVE AGENCY LLC, AS ADMINISTRATIVE AGENT
Reel/Frame 067000/0669 →
PATENT SECURITY AGREEMENT Recorded Aug 1, 2023
From: R.R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS 2028 NOTES COLLATERAL AGENT
Reel/Frame 064463/0597 →
PATENT SECURITY AGREEMENT Recorded Aug 1, 2023
From: R.R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 064462/0445 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, PREVIOUSLY RECORDED AT REEL 056079, FRAME 0534 Recorded Jul 31, 2023
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
Reel/Frame 064441/0646 →
ASSIGNMENT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL RECORDED AT REEL/FRAME 056122/0839 AND 059203/0333 Recorded Apr 28, 2023
From: JEFFERIES FINANCE LLC
To: APOLLO ADMINISTRATIVE AGENCY LLC
Reel/Frame 063487/0449 →
INTELLECTUAL PROPERTY ASSIGNMENT AGREEMENT Recorded Feb 10, 2023
From: BANK OF AMERICA, N.A.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 062702/0648 →
ASSIGNMENT OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL RECORDED AT R/F 056122/0839 Recorded Feb 25, 2022
From: BANK OF AMERICA, N.A.
To: JEFFERIES FINANCE LLC
Reel/Frame 059203/0333 →
SECURITY INTEREST Recorded May 3, 2021
From: R. R. DONNELLEY & SONS COMPANY
To: BANK OF AMERICA, N.A.
Reel/Frame 056122/0810 →
SECURITY INTEREST Recorded May 3, 2021
From: R. R. DONNELLEY & SONS COMPANY
To: BANK OF AMERICA, N.A.
Reel/Frame 056122/0839 →
SECURITY INTEREST Recorded Apr 28, 2021
From: R. R. DONNELLEY & SONS COMPANY; CONSOLIDATED GRAPHICS, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 056079/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2016
From: CYMAN, THEODORE F., JR; LEE, NANCY A.; CAMERON, ALI K.; PALMER, ERIC V.
To: R.R. DONNELLEY & SONS COMPANY
Reel/Frame 037736/0142 →