MTP-thyristor memory cell circuits and methods of operation
View Patent ↗An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.
1. In an integrated circuit having an array of memory cells, each memory cell capable of holding information by the storage of charge and comprising:
a thyristor having anode and cathode regions and two intermediate regions therebetween;
an MTP device connected to one of the two intermediate regions of the thyristor and having a charge storage region, the charge in the charge storage region determining the threshold voltage of the MTP device and controlling the switching of the thyristor;
whereby the information held in the memory cell is determined using the switching of the thyristor.
2. The memory cell of claim 1 wherein the charge storage region comprises a charge trapping region.
3. The memory cell of claim 2 wherein the charge trapping region comprises a sidewall charge trapping region.
4. The memory cell of claim 2 wherein the charge trapping region comprises a silicon nitride layer.
5. The memory cell of claim 4 wherein the silicon nitride layer is formed within a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon layers) structure.
6. The memory cell of claim 1 wherein the MTP device comprises a first source/drain region connected to the one of the two intermediate regions of the thyristor, a second source/drain region connected to a bit line; and a gate connected to a first word line; and wherein the thyristor anode region is connected to an anode line and the thyristor cathode region is connected to the bit line.
7. The memory cell of claim 6 wherein the first and second source/drain regions comprise N-doped regions.
8. The memory cell of claim 6 wherein the first and second source/drain regions comprise P-doped regions.
9. The memory cell of claim 6 further comprising:
a MOSFET having a first source/drain region connected to a first Program/Erase line, a second source/drain region connected to the first MTP device source/drain region, and a gate connected to a second Program/Erase line, wherein the MOSFET provides a path for Programming and Erasing the MTP device.
10. The memory cell of claim 9 wherein a channel region beneath the gate of the MTP device is connected to a third Program/Erase line.
11. The memory cell of claim 9 wherein the well region connected to a fourth Program/Erase line.
12. The memory cell of claim 9 wherein the MOSFET comprises an NMOS transistor.
13. The memory cell of claim 9 wherein the MOSFET comprises a PMOS transistor.