Equalizer
An equalizer includes a data sampler that samples input data and outputs a time-series data string according to the input data, an arithmetic circuit that multiplies a data string output before reference data in the data string output from the data sampler by a tap coefficient and forms the input data by an arithmetic operation of a multiplication result and an input signal, a tap coefficient calculation circuit that updates the tap coefficient based on a data string output before the reference data, and a determination circuit that receives the reference data and data output after the reference data in the data string and controls presence or absence of update of the tap coefficient performed by the tap coefficient calculation circuit.
1. An equalizer including an input buffer that receives an input signal, a decision feedback equalizer including a data sampler and an error sampler, and a tap coefficient calculation circuit that receives a data output from the data sampler and an error output from the error sampler and adaptively calculates a tap coefficient in the decision feedback equalizer, the equalizer comprising:
a filter circuit that receives data of a predetermined first symbol as reference data and data of a second symbol after the predetermined first symbol in the data output from the data sampler,
wherein an update of the tap coefficient in the tap coefficient calculation circuit is determined according to a result of the filter circuit, and
wherein the filter circuit performs an exclusive OR operation between the first symbol and the second symbol, and, when an operation result of the exclusive OR operation indicates coincidence, the filter circuit causes the tap coefficient in the tap coefficient calculation circuit to be updated.
2. The equalizer according to claim 1 , wherein the filter circuit receives an enable signal that disables updating of the tap coefficient in in the tap coefficient calculation circuit.
3. The equalizer according to claim 1 , wherein the filter circuit receives the reference data and data of a plurality of symbols after the predetermined symbol.
4. The equalizer according to claim 1 , wherein the error sampler performs sampling based on an offset coefficient from the tap coefficient calculation circuit, and the filter circuit causes the offset coefficient in the tap coefficient calculation circuit to be updated.
5. The equalizer according to claim 4 , wherein, when the operation result of the exclusive OR operation indicates coincidence, the filter circuit causes the offset coefficient in the tap coefficient calculation circuit to be updated, and the tap coefficient calculation circuit updates the offset coefficient based on the first symbol and the error output from the error sampler.
6. The equalizer according to claim 1 , wherein, when the operation result of the exclusive OR operation indicates non-coincidence, the filter circuit prohibits the tap coefficient in the tap coefficient calculation circuit from being updated.
7. An equalizer including an input buffer that receives an input signal, a decision feedback equalizer including a data sampler and an error sampler, and a tap coefficient calculation circuit that receives a data output from the data sampler and an error output from the error sampler and adaptively calculates a tap coefficient in the decision feedback equalizer, the equalizer comprising:
a filter circuit that receives data of a predetermined first symbol as reference data and data of a second symbol after the predetermined first symbol in the data output from the data sampler,
wherein an update of the tap coefficient in the tap coefficient calculation circuit is determined according to a result of the filter circuit, and
wherein the filter circuit performs an exclusive NOR operation between the first symbol and the second symbol, and, when an operation result of the exclusive NOR operation indicates non-coincidence, the filter circuit causes the tap coefficient in the tap coefficient calculation circuit to be updated.
8. The equalizer according to claim 7 , wherein the filter circuit receives an enable signal that disables updating of the tap coefficient in in the tap coefficient calculation circuit.
9. The equalizer according to claim 7 , wherein the filter circuit receives the reference data and data of a plurality of symbols after the predetermined symbol.
10. The equalizer according to claim 7 , wherein the error sampler performs sampling based on an offset coefficient from the tap coefficient calculation circuit, and the filter circuit causes the offset coefficient in the tap coefficient calculation circuit to be updated.
11. The equalizer according to claim 10 , wherein, when the operation result of the exclusive NOR operation indicates non-coincidence, the filter circuit causes the offset coefficient in the tap coefficient calculation circuit to be updated, and the tap coefficient calculation circuit updates the offset coefficient based on the first symbol and the error output from the error sampler.
12. The equalizer according to claim 7 , wherein, when the operation result of the exclusive NOR operation indicates coincidence, the filter circuit prohibits the tap coefficient in the tap coefficient calculation circuit from being updated.
13. An equalizer including an input buffer that receives an input signal, a decision feedback equalizer including a data sampler and an error sampler, and a tap coefficient calculation circuit that receives a data output from the data sampler and an error output from the error sampler and adaptively calculates a tap coefficient in the decision feedback equalizer, the equalizer comprising:
a filter circuit that receives data of a predetermined first symbol as reference data and data of a second symbol after the predetermined first symbol in the data output from the data sampler,
wherein the error sampler performs sampling based on an offset coefficient from the tap coefficient calculation circuit,
wherein an update of the tap coefficient and an update of the offset coefficient in the tap coefficient calculation circuit are determined according to a result of the filter circuit based on the first symbol and the second symbol.
14. The equalizer according to claim 13 , wherein the filter circuit performs an exclusive OR operation between the first symbol and the second symbol, and, when an operation result of the exclusive OR operation indicates coincidence, the filter circuit causes the tap coefficient and the offset coefficient in the tap coefficient calculation circuit to be updated.
15. The equalizer according to claim 13 , wherein the filter circuit performs an exclusive NOR operation between the first symbol and the second symbol, and when an operation result of the exclusive NOR operation indicates non-coincidence, the filter circuit causes the tap coefficient and the offset coefficient in the tap coefficient calculation circuit to be updated.
16. The equalizer according to claim 13 , wherein the filter circuit receives an enable signal that disables updating of the tap coefficient in in the tap coefficient calculation circuit.
17. The equalizer according to claim 13 , wherein the filter circuit receives the reference data and data of a plurality of symbols after the predetermined symbol.
18. The equalizer according to claim 13 , wherein the tap coefficient calculation circuit updates the offset coefficient based on the first symbol and the error output from the error sampler.
19. The equalizer according to claim 14 , wherein, when the operation result of the exclusive OR operation indicates non-coincidence, the filter circuit prohibits the tap coefficient and the offset coefficient in the tap coefficient calculation circuit from being updated.
20. The equalizer according to claim 15 , wherein, when the operation result of the exclusive NOR operation indicates coincidence, the filter circuit prohibits the tap coefficient and the offset coefficient in the tap coefficient calculation circuit from being updated.