Bit line equalizer

1. A bit line equalizer comprising:

a first gate extended in a first direction;

a second gate spaced apart from the first gate by a predetermined distance, and extended parallel to the first gate;

a third gate configured to interconnect the first gate and the second gate;

a first contact node located at one side of the first gate;

a second contact node located at one side of the second gate;

a third contact node located between the first gate and the second gate, and located at one side of the third gate; and

a fourth contact node located between the first gate and the second gate, and located at an other side of the third gate,

wherein the first and second gates are line shaped, and

wherein the first, second and third gates are disposed in a single active region.

2. The bit line equalizer according to claim 1 , wherein the third gate is located between the first gate and the second gate, and interconnects a center part of the first gate and a center part of the second gate, extending in a second direction perpendicular to the first direction.

3. The bit line equalizer according to claim 1 , wherein the first contact node is coupled to a bit line.

4. The bit line equalizer according to claim 1 , wherein the second contact node is coupled to an inverted bit line of the bit line.

5. The bit line equalizer according to claim 1 , wherein the first gate and the second gate are disposed between the first contact node and the second contact node.

6. The bit line equalizer according to claim 5 , wherein the first contact node and the second contact node are symmetrical to each other wherein the line of symmetry is a line cutting through the middle of the third gate in the first direction.

7. A bit line equalizer comprising:

a first gate extended in a first direction;

a second gate spaced apart from the first gate by a predetermined distance, and extended parallel to the first gate;

a third gate configured to interconnect the first gate and the second gate;

at least one first contact node located at one side of the first gate;

at least one second contact node located at one side of the second gate; and

a third contact node located between the first gate and the second gate, and located at one side of the third gate,

wherein the first and second gates are line shaped, and

wherein the first, second and third gates are disposed in a single active region.

8. The bit line equalizer according to claim 7 , wherein the third gate is located between the first gate and the second gate, and interconnects a center part of the first gate and a center part of the second gate, extending in a second direction perpendicular to the first direction.

9. The bit line equalizer according to claim 7 , wherein the first contact node is coupled to a bit line.

10. The bit line equalizer according to claim 7 , wherein the second contact node is coupled to an inverted bit line of the bit line.

11. The bit line equalizer according to claim 7 , wherein the first gate and the second gate are disposed between the first contact node and the second contact node.

12. The bit line equalizer according to claim 11 , wherein the first contact node and the second contact node are symmetrical to each other wherein the line of symmetry is a line cutting through the middle of the third gate in the first direction.

13. A bit line equalizer comprising:

a first active region;

a second active region;

a first gate extended in a first direction such that the first gate is formed across the first active region and the second active region;

a second gate spaced apart from the first gate by a predetermined distance, and extended parallel to the first gate such that the second gate is formed across the first active region and the second active region;

a third gate located in the first active region, and configured to interconnect the first gate and the second gate;

a fourth gate located in the second active region, and configured to interconnect the first gate and the second gate;

first contact nodes located in the first active region, and located at both sides so that the first and second gates are interposed therebetween;

second contact nodes located in the second active region, and located at both sides so that the first and second gates are interposed therebetween;

third contact nodes located in the first active region, and located at both sides of the third gate; and

fourth contact nodes located in the second active region, and located at both sides of the fourth gate,

wherein the first and second gates are line shaped.

14. The bit line equalizer according to claim 13 , wherein:

the first contact nodes are coupled to a first pair of bit lines; and

the second contact nodes are coupled to a second pair of bit lines.

15. The bit line equalizer according to claim 13 , further comprising:

a coupling unit configured to interconnect the first active region and the second active region.

16. The bit line equalizer according to claim 15 , wherein the coupling unit is disposed between the third contact nodes and the fourth contact nodes.