Memory system having idle-memory devices and method of operating thereof
View Patent ↗The memory system may include a memory device including a plurality of sub-memory devices coupled to a channel; and a controller suitable for controlling the memory device to store a first data into a selected sub-memory device and at least one idle sub-memory device among the sub-memory devices during a first program operation to a selected sub-memory device among the sub-memory devices with the first data with a first data; and to perform a second program operation to the selected sub-memory device with the first data stored in the idle sub-memory device when the first program operation to the selected sub-memory device fails.
1. A memory system, comprising:
a memory device including a plurality of sub-memory devices coupled to a channel; and
a controller suitable for controlling the memory device to store a first data into a selected sub-memory device and at least one idle sub-memory device among the sub-memory devices when a first program operation of the selected sub-memory device among the sub-memory devices with the first data is performed; and to perform a second program operation to the selected sub-memory device with the first data stored in the idle sub-memory device when the first program operation to the selected sub-memory device fails.
2. The memory system of claim 1 , wherein each sub-memory devices includes a page buffer suitable for storing the first data.
3. The memory system of claim 1 , wherein the controller inputs the first data into the selected sub-memory device and the idle sub-memory device at the same time.
4. The memory system of claim 1 , wherein the controller comprises a buffer memory for storing data temporarily.
5. The memory system of claim 4 , wherein the controller transfers the first data from the idle sub-memory device to the selected sub-memory through the buffer memory for the second program operation when the first program operation to the selected sub-memory fails.
6. The memory system of claim 5 , wherein the controller controls a peripheral circuit to perform the second program operation to the selected sub-memory device by changing an address indicating another memory area of the selected sub-memory device for the second program operation.
7. The memory system of claim 1 , wherein the controller provides an address to the selected and the idle sub-memory devices before storing the first data in the idle sub-memory device.
8. The memory system of claim 1 , wherein the idle sub-memory device is coupled to the channel same as that of the selected sub-memory device.
9. The memory system of claim 1 , wherein the controller resets a page buffer, in which the first data is stored, of the idle sub-memory device when the first program operation of the sub-memory device is successful.
10. The memory system of claim 1 , wherein when the first data are stored in a plurality of the idle sub-memory devices and a read operation is performed on one of the idle sub-memory devices, the controller resets a page buffer of the idle sub-memory device on which the read operation is to be performed in response to a new command as long as the at least one idle sub-memory device in which the first data is stored remains.
11. A method of operating a memory system comprising:
inputting first data into a first sub-memory device and a second sub-memory device coupled to a same channel;
performing a first program operation of the first sub-memory device with the first data inputted into the first sub-memory device; and
performing a second program operation to the first sub-memory device with the first data stored in the second sub-memory device when the first program operation fails.
12. The method of claim 11 , further comprises deleting the first data from the second sub-memory device when the first program operation is successful.
13. The method of claim 11 , wherein the first program operation is performed to a selected page of a selected memory block, among memory blocks in the first sub-memory device.
14. The method of claim 13 , wherein the performing of the second program operation includes changing an address indicating another memory area of the selected sub-memory device for the second program operation.
15. The method of claim 14 , wherein the address indicates one or more of a page and a memory block included in the first sub-memory device.
16. A method of operating a memory system, comprising:
inputting a program command for a first program operation of a first sub-memory device into the first sub-memory device and a second sub-memory devices;
inputting an address and a first data for the first program operation into the first and second sub-memory devices;
inputting a program start command for the first program operation into the first sub-memory device; and
inputting a program holding command to the second sub-memory device to stay idle during the first program operation.
17. The method of claim 16 , wherein each of inputting of the program command and the inputting of the address and the first data comprises:
inputting active chip enable signals to the first and second sub-memory devices, and
inputting inactive chip enable signals to remaining sub-memory devices, except for the first and second sub-memory devices.
18. The method of claim 16 , wherein the inputting of the program start command comprises:
inputting an active chip enable signal to the first sub-memory device, and
inputting an inactive chip enable signal to the second sub-memory device.
19. The method of claim 16 , wherein the inputting of the program holding command comprises:
inputting an inactive chip enable signal to the first sub-memory device, and
inputting an active chip enable signal to the second sub-memory device.
20. The method of claim 16 , further comprises:
performing a second program operation to the first sub-memory device with the first data stored in the second sub-memory device when the first program operation fails.