IP Library Granted Patent US 9,875,051
Granted Patent B2
US 9,875,051 · App. 15/049,756 · Granted Jan 23, 2018

Memory system that controls power state of buffer memory

Inventor: Hirotaka Suzuki (Kawasaki Kanagawa, JP)
Assignee: Toshiba Memory Corporation
G06F3/0625G06F1/3275G06F1/3287G06F3/061G06F3/0655G06F3/0688G06F12/00G11C5/148G11C11/005G11C11/417G11C16/10Y02B60/1228Y02B60/1282
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Quick Facts
Patent No.
US 9,875,051
App. No.
15/049,756
Granted
Jan 23, 2018
Kind
B2
Abstract

A memory device includes a nonvolatile memory unit, a volatile memory unit including first and second memory modules, and a controller configured to store data from the nonvolatile memory unit in the volatile memory unit before the data are transferred to a host. While the controller stores the data in the first memory module, the first memory module is in a first power state and the second memory module is in a second power state. The first power state corresponds to a high power consumption state and the second power state corresponds to a low power consumption state.

Claims (39)

1. A memory device, comprising:

a nonvolatile memory unit;

a volatile memory unit including first and second memory modules; and

a controller configured to store data from the nonvolatile memory unit in the volatile memory unit before the data are transferred to a host, wherein

while the controller stores the data in the first memory module, the first memory module is in a first power state and the second memory module is in a second power state, the first power state corresponding to a high power consumption state and the second power state corresponding to a low power consumption state.

2. The memory device according to claim 1 , wherein

the first memory module is moved to the second power state upon completion of the storing of the data in the first memory module.

3. The memory device according to claim 1 , wherein

the controller is configured to start a process to store the data in the first memory module a predetermined time after the first memory module is moved to the first power state.

4. The memory device according to claim 1 , wherein

the controller is configured to store additional data from the nonvolatile memory unit in the first memory module consecutively after and upon completion of the storing of the data in the first memory module, while maintaining the first memory module in the first power state.

5. The memory device according to claim 1 , wherein

the controller is further configured to move the second memory module into the first power state while the data is being stored in the first memory module, and store additional data from the nonvolatile memory unit in the second memory module upon completion of the storing of the data in the first memory module.

6. The memory device according to claim 1 , wherein

while the data stored in the first memory module is transferred to the host, the first memory module is in the first power state and the second memory module is in the second power state.

7. The memory device according to claim 6 , wherein

while the data is being transferred from the first memory module to the host, the second memory module is moved to the first power state, and

data stored in the second memory module is transferred to the host upon completion of the transferring of the data from the first memory module to the host.

8. The memory device according to claim 7 , wherein

the controller stores the data in the second memory module after storing the data in the first memory module.

9. The memory device according to claim 1 , wherein

each of the first and second memory modules has a capacity that is equal to an integer multiple of a unit size of data processed by the host.

10. The memory device according to claim 1 , wherein

the first power state is a power-on state, and the second power state is a power-off state.

11. A memory device, comprising:

a nonvolatile memory unit;

a volatile memory unit including first and second memory modules; and

a controller configured to store data from the nonvolatile memory unit in the volatile memory unit before the data are transferred to a host, wherein

while the controller transfers data in the first memory module to the host, the first memory module is in a first power state and the second memory module in a second power state, the first power state corresponding to a high power consumption state and the second power state corresponding to a low power consumption state.

12. The memory device according to claim 11 , wherein

the first memory module is moved to the second power state upon completion of the transferring of the data from the first memory module to the host.

13. The memory device according to claim 11 , wherein

the controller is configured to start a process to transfer the data in the first memory module to the host a predetermined time after the first memory module is moved to the first power state.

14. The memory device according to claim 11 , wherein

the controller is configured to move the second memory module into the first power state while the data is being transferred from the first memory module to the host, and transfer data stored in the second memory module to the host upon completion of the transferring of the data stored in the first memory module to the host.

15. The memory device according to claim 14 , wherein

the controller stores the data in the second memory module after storing the data in the first memory module.

16. The memory device according to claim 11 , wherein

the first power state is a power-on state, and the second power state is a power-off state.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2016
From: SUZUKI, HIROTAKA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037788/0466 →
Continuity (2)
Provisional Application 62152210 · Apr 24, 2015
Related Publication 20160313941A1 · Oct 27, 2016