Semiconductor integrated circuit device having low and high withstanding-voltage MOS transistors
View Patent ↗A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.
1. A semiconductor integrated circuit device, comprising:
an N-channel type low withstanding-voltage MOS transistor formed in a first P-type well region formed in an N-type semiconductor substrate, the N-channel type low withstanding-voltage MOS transistor comprising:
a first gate insulating film;
a first gate electrode made of polycrystalline silicon;
a first N-type high-concentration drain region and a first N-type high-concentration source region each including an N-type high-concentration impurity region; and
a first N-type low-concentration drain region formed between the first gate electrode and the first N-type high-concentration drain region and a first N-type low-concentration source region formed between the first gate electrode and the first N-type high-concentration source region;
a P-channel type low-withstanding voltage MOS transistor formed in an N-type well region formed in a region different from the first P-type well region so as to be in contact with the first P-type well region, the P-channel type low-withstanding voltage MOS transistor comprising:
a second gate insulating film;
a second gate electrode made of polycrystalline silicon;
a P-type high-concentration drain region and a P-type high-concentration source region each including a P-type high-concentration impurity region; and
a P-type low-concentration drain region formed between the second gate electrode and the P-type high-concentration drain region and a P-type low-concentration source region formed between the second gate electrode and the P-type high-concentration source region;
a first N-channel type high withstanding-voltage MOS transistor formed in a second P-type well region that is prevented from being in contact with the first P-type well region and has the same impurity concentration as an impurity concentration of the first P-type well region, the first N-channel type high withstanding-voltage MOS transistor comprising:
a third gate insulating film;
a third gate electrode made of polycrystalline silicon;
a third N-type high-concentration drain region and a third N-type high-concentration source region each including an N-type high-concentration impurity region;
a second N-type low-concentration drain region formed between the third gate electrode and the third N-type high-concentration drain region and a second N-type low-concentration source region formed between the third gate electrode and the third N-type high-concentration source region;
an insulating film that has a thickness larger than a thickness of the third gate insulating film, and is formed on the second N-type low-concentration drain region and the second N-type low-concentration source region; and
a third N-type low-concentration impurity region formed below a region including a part of the second N-type low-concentration drain region and the third N-type high-concentration drain region so that the third N-type low-concentration impurity region has a depth smaller than a depth of the second P-type well region; and
a second N-channel high withstanding-voltage MOS transistor.
2. A semiconductor integrated circuit device according to claim 1 , wherein the second N-channel type high withstanding-voltage MOS transistor comprises an ESD protection element and has the same configuration as a configuration of the first N-channel type high withstanding-voltage MOS transistor.
3. A semiconductor integrated circuit device according to claim 1 , wherein:
the second N-channel type high withstanding-voltage MOS transistor is formed in a third P-type well region that is prevented from being in contact with the first P-type well region and has the same impurity concentration as the impurity concentration of the first P-type well region, the second N-channel type high withstanding-voltage MOS transistor comprising:
a fourth gate insulating film;
a fourth gate electrode made of polycrystalline silicon
a fourth N-type high-concentration drain region and a fourth N-type high-concentration source region each including an N-type high-concentration impurity region;
a third N-type low-concentration drain region formed between the fourth gate electrode and the fourth N-type high-concentration drain region and a third N-type low-concentration source region formed between the fourth gate electrode and the fourth N-type high-concentration source region;
an insulating film that has a thickness larger than a thickness of the fourth gate insulating film, and is formed on the third N-type low-concentration drain region and the third N-type low-concentration source region; and
a fourth N-type low-concentration impurity region that includes a part of the third N-type low-concentration drain region and the fourth N-type low-concentration drain region, is formed so as to be adjacent to the third P-type well region, and has a bottom surface being in contact with the N-type semiconductor substrate; and
the second N-channel type high withstanding-voltage MOS transistor is used as an ESD protection element.
4. A semiconductor integrated circuit device, comprising:
a first P-type well region formed in an N-type semiconductor substrate;
an N-channel type low withstanding-voltage MOS transistor formed in a second P-type well region having an impurity concentration higher than an impurity concentration of the first P-type well region;
a P-channel type low withstanding-voltage MOS transistor formed in an N-type well region;
a first N-channel type high withstanding-voltage MOS transistor formed in a third P-type well region that is prevented from being in contact with the second P-type well region and has the same impurity concentration as an impurity concentration of the second P-type well region, the first N-channel type high withstanding-voltage MOS transistor comprising:
a first gate insulating film;
a first gate electrode made of polycrystalline silicon;
a first N-type high-concentration drain region and a first N-type high-concentration source region each including an N-type high-concentration impurity region;
a first N-type low-concentration drain region formed between the first electrode and the first N-type high-concentration drain region and a first N-type low-concentration source region formed between the first gate electrode and the first N-type high-concentration source region;
an insulating film that has a thickness larger than a thickness of the first gate insulating film, and is formed on the first N-type low-concentration drain region and the first N-type low-concentration source region; and
a third N-type low-concentration impurity region formed below a part of the first N-type low-concentration drain region and the first N-type high-concentration drain region so that the third N-type low-concentration impurity region has a depth smaller than a depth of the third P-type well region, the first P-type well region being formed below the third N-type low-concentration impurity region and between the third N-type low-concentration impurity region and the N-type semiconductor substrate; and
a second N-channel type high withstanding-voltage MOS transistor formed in a fourth P-type well region that is prevented from being in contact with the second P-type well region and has the same impurity concentration as an impurity concentration of the second P-type well region, the second N-channel type high withstanding-voltage MOS transistor comprising:
a second gate insulating film;
a second gate electrode made of polycrystalline silicon;
a second N-type high-concentration drain region and a second N-type high-concentration source region each including an N-type high-concentration impurity region;
a second N-type low-concentration drain region formed between the second gate electrode and the second N-type high-concentration drain region and a second N-type low-concentration source region formed between the second gate electrode and the second N-type high-concentration source region;
an insulating film that has a thickness larger than a thickness of the second gate insulating film, and is formed on the second N-type low-concentration drain region and the second N-type low-concentration source region; and
a fourth N-type low-concentration impurity region that includes a part of the second N-type low-concentration drain region and the second N-type high-concentration drain region, is formed so as to be adjacent to the fourth P-type well region, and has a bottom surface being in contact with the N-type semiconductor substrate,
the second N-channel type high withstanding-voltage MOS transistor being used as an ESD protection element.
5. A semiconductor integrated circuit device according to claim 1 , wherein:
a drain terminal of the second N-channel type high withstanding-voltage MOS transistor is connected to a power supply terminal;
a gate terminal and a source terminal of the second N-channel type high withstanding-voltage MOS transistor are connected to a ground terminal; and
the second N-channel type high withstanding-voltage MOS transistor is used as an ESD protection element.
6. A semiconductor integrated circuit device according to claim 4 , wherein:
a drain terminal of the second N-channel type high withstanding-voltage MOS transistor is connected to a power supply terminal;
a gate terminal and a source terminal of the second N-channel type high withstanding-voltage MOS transistor are connected to a ground terminal; and
the second N-channel type high withstanding-voltage MOS transistor is used as an ESD protection element.
7. A semiconductor integrated circuit device according to claim 1 , wherein:
the N-type semiconductor substrate contains phosphorous at an impurity concentration of 3×10 14 /cm 3 to 8×10 14 /cm 3 ;
the first P-type well region contains one of boron and BF2 at an impurity concentration of 8×10 15 /cm 3 to 8×10 16 /cm 3 and has a depth of from 7 μm to 10 μm from a surface of the semiconductor substrate;
the N-type well region contains phosphorous at an impurity concentration of 8×10 15 /cm 3 to 4×10 16 /cm 3 and has a depth of from 7 μm to 10 μm from the surface of the semiconductor substrate; and
the third N-type low-concentration impurity region contains arsenic at an impurity concentration of 2×10 16 /cm 3 to 2×10 17 /cm 3 and has a depth of from 2 μm to 3.5 μm from the surface of the semiconductor substrate.
8. A semiconductor integrated circuit device according to claim 4 , wherein:
the N-type semiconductor substrate contains phosphorous at an impurity concentration of 3×10 14 /cm 3 to 8×10 14 /cm 3 ;
the first P-type well region contains one of boron and BF 2 at an impurity concentration of 8×10 15 /cm 3 to 8×10 16 /cm 3 and has a depth of from 7 μm to 10 μm from a surface of the semiconductor substrate;
the N-type well region contains phosphorous at an impurity concentration of 8×10 15 /cm 3 to 4×10 16 /cm 3 and has a depth of from 7 μm to 10 μm from the surface of the semiconductor substrate; and
the third N-type low-concentration impurity region contains arsenic at an impurity concentration of 2×10 16 /cm 3 to 2×10 17 /cm 3 and has a depth of from 2 μm to 3.5 μm from the surface of the semiconductor substrate.
9. A semiconductor integrated circuit device according to claim 7 , wherein a minimum gate length of the N-channel type low withstanding-voltage MOS transistor is 1.0 μm.
10. A semiconductor integrated circuit device according to claim 8 , wherein a minimum gate length of the N-channel type low withstanding-voltage MOS transistor is 1.0 μm.
11. A semiconductor integrated circuit device according to claim 4 , wherein the second P-type well region contains one of boron and BF 2 at an impurity concentration of 5×10 16 /cm3 to 2×10 17 /cm 3 .
12. A semiconductor integrated circuit device according to claim 4 , wherein a minimum gate length of the N-channel type low withstanding-voltage MOS transistor is 0.5 μm.