Semiconductor memory device

1. A semiconductor memory device comprising:

a first block including a first memory string that includes a first memory cell transistor and a first select transistor;

a second block including a second memory string that includes a second memory cell transistor and a second select transistor;

a first select gate line that is electrically connected to a gate of the first select transistor; and

a second select gate line that is electrically connected to a gate of the second select transistor,

wherein during writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.

2. The device according to claim 1 , further comprising:

a first bit line electrically connected to a first end of the first memory string and a first end of the second memory string;

a second bit line electrically connected to a first end of a third memory string in the first block and a first end of a fourth memory string in the second block;

a first sense amplifier having a first transistor that is turned on and off to electrically connect and disconnect an internal node of the first sense amplifier and the first bit line; and

a second sense amplifier having a second transistor that is turned on and off to electrically connect and disconnect an internal node of the second sense amplifier and the second bit line, wherein

the first transistor is turned on during the first time period and turned off during the second time period.

3. The device according to claim 2 , wherein the second transistor is turned on during the first time period and the second time period.

4. The device according to claim 3 , further comprising:

a source line that is electrically connected to second ends of the first, second, third, and fourth memory strings,

wherein during the second time period, voltages applied to the second bit line, the source line, and the second select gate line are increased.

5. The device according to claim 4 , wherein

the voltage applied to the second bit line is decreased during a fourth time period after the third time period, while the voltages applied to the source line and the second select gate line are maintained.

6. The device according to claim 2 , wherein

during the writing of data and prior to the first time period, the first voltage is applied to the first and second bit lines and then during the first time period, the first bit line is maintained at the first voltage while the second bit line is discharged.

7. The device according to claim 1 , further comprising:

a first word line that is electrically connected to a gate of the first memory cell transistor; and

a second word line that is electrically connected to a gate of the second memory cell transistor, wherein

during the writing of data, a fourth voltage higher than any of the first, second, and third voltages is applied to the first word line while the third voltage is applied to the first select gate line.

8. The device according to claim 7 , wherein

during the writing of data and while the third voltage is applied to the first select gate line, a fifth voltage that is lower than the fourth voltage but higher than any of the first, second, and third voltages is applied to the first and second word lines before the fourth voltage is applied to the first word line.

9. The device according to claim 1 , wherein the first and second blocks include a plurality of memory cell transistors that are arranged on a plane.

10. The device according to claim 1 , wherein the first and second blocks include a plurality of memory cell transistors that are three-dimensionally arranged above a well region.

11. A method of writing data in a semiconductor memory device including a first block including a first memory string that includes a first memory cell transistor and a first select transistor, a second block including a second memory string that includes a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor, said method comprising:

performing a coarse writing operation to a memory cell transistor in the first block; and then

performing a fine writing operation to the memory cell transistor, wherein

at least one of the coarse and fine writing operations include the steps of:

applying a first voltage to the first select gate line during a first time period;

applying a second voltage to the second select gate line during a second time period after the first time period; and

applying a third voltage lower than the first voltage to the first select gate line during a third time period after the second time period.

12. The method according to claim 11 , wherein the semiconductor memory device further comprises:

a first bit line electrically connected to a first end of the first memory string and a first end of the second memory string;

a second bit line electrically connected to a first end of a third memory string in the first block and a first end of a fourth memory string in the second block;

a first sense amplifier having a first transistor that is turned on and off to electrically connect and disconnect an internal node of the first sense amplifier and the first bit line; and

a second sense amplifier having a second transistor that is turned on and off to electrically connect and disconnect an internal node of the second sense amplifier and the second bit line, wherein

the first transistor is turned on during the first time period and turned off during the second time period.

13. The method according to claim 12 , wherein the second transistor is turned on during the first time period and the second time period.

14. The method according to claim 13 , wherein the semiconductor memory device further comprises:

a source line that is electrically connected to second ends of the first, second, third, and fourth memory strings,

wherein during the second time period, voltages applied to the second bit line, the source line, and the second select gate line are increased.

15. The method according to claim 14 , wherein

the voltage applied to the second bit line is decreased during a fourth time period after the third time period, while the voltages applied to the source line and the second select gate line are maintained.

16. The method according to claim 12 , wherein

during the writing of data and prior to the first time period, the first voltage is applied to the first and second bit lines and then during the first time period, the first bit line is maintained at the first voltage while the second bit line is discharged.

17. The method according to claim 11 , wherein the semiconductor memory device further comprises:

a first word line that is electrically connected to a gate of the first memory cell transistor; and

a second word line that is electrically connected to a gate of the second memory cell transistor, wherein

during the writing of data, a fourth voltage higher than any of the first, second, and third voltages is applied to the first word line while the third voltage is applied to the first select gate line.

18. The method according to claim 17 , wherein

during the writing of data and while the third voltage is applied to the first select gate line, a fifth voltage that is lower than the fourth voltage but higher than any of the first, second, and third voltages is applied to the first and second word lines before the fourth voltage is applied to the first word line.

19. The method according to claim 11 , wherein the first and second blocks include a plurality of memory cell transistors that are arranged on a plane.

20. The method according to claim 11 , wherein the first and second blocks include a plurality of memory cell transistors that are three-dimensionally arranged above a well region.