IP Library Granted Patent US 9,773,697
Granted Patent B2
US 9,773,697 · App. 15/054,855 · Granted Sep 26, 2017

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 9,773,697
App. No.
15/054,855
Granted
Sep 26, 2017
Kind
B2
Abstract

According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.

Claims (37)

1. A method of manufacturing a semiconductor device, comprising:

forming a first insulating layer on a first surface of a semiconductor substrate comprising silicon;

forming a conductive layer on the first insulating layer;

forming a first opening that extends from a second surface of the semiconductor substrate opposite to the first surface toward the first surface, the first opening extending in the semiconductor substrate to the first insulating layer;

performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening;

forming a second insulating layer on a side wall of the semiconductor substrate in the first opening;

performing a second annealing process after formation of the second insulating layer;

forming a second opening that extends in the first insulating layer to the conductive layer through the first opening; and

forming a through-via in the first and second openings that is connected to the conductive layer.

2. The method according to claim 1 ,

wherein the second annealing process is performed in a second gas atmosphere that contains hydrogen.

3. The method according to claim 2 ,

wherein a first hydrogen region is formed in the semiconductor substrate by the first annealing process.

4. The method according to claim 2 ,

wherein the first and second annealing processes are performed using a hydrogen radical or deuterium.

5. The method according to claim 4 ,

wherein a first hydrogen region is formed in the semiconductor substrate by the first annealing process.

6. The method according to claim 1 ,

wherein a first hydrogen region is formed in the semiconductor substrate by the first annealing process.

7. The method according to claim 1 ,

wherein the through-via has a width dimension at the second surface that is equal to or greater than a width dimension of the second opening.

8. A method of manufacturing a semiconductor device, comprising:

forming a first insulating layer on a first surface of a semiconductor substrate comprising silicon;

forming a conductive layer on the first insulating layer;

forming a first opening in the semiconductor substrate, the first opening extending from a second surface of the semiconductor substrate that is opposite the first surface, toward the first surface to reach the first insulating layer;

forming a second insulating layer on a side wall of the first opening in the semiconductor substrate;

performing an annealing process after formation of the second insulating layer;

forming a second opening, which extends to the conductive layer, in the first insulating layer through the first opening; and

forming a through-via in the first and second openings which is connected to the conductive layer.

9. The method according to claim 8 , further comprising:

performing an annealing process in an atmosphere that contains hydrogen after formation of the first opening.

10. The method according to claim 8 ,

wherein the annealing process is performed using a hydrogen radical or deuterium.

11. The method according to claim 8 ,

wherein a first hydrogen region is formed in the side wall of the first opening in semiconductor substrate by the first annealing process.

12. The method according to claim 8 ,

wherein the through-via has a width dimension at the second surface which is equal to or greater than a width dimension at the first opening.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2016
From: TSUKIYAMA, SATOSHI; SETO, MOTOSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038780/0102 →