IP Library › Granted Patent US 9,941,901
Granted Patent B2
US 9,941,901 · App. 15/055,006 · Granted Apr 10, 2018

Systems and methods for soft decision generation in a solid state memory system

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Quick Facts
Patent No.
US 9,941,901
App. No.
15/055,006
Granted
Apr 10, 2018
Kind
B2
Abstract

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.

Claims (36)

1. A data storage system, the system comprising:

a solid state memory device;

a soft data generation circuit operable to:

receive multiple instances of an element of a read data set accessed from the solid state memory device; and

access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data;

a data de-randomizer circuit operable to de-randomize the soft data, wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element, wherein a first portion of the soft data values corresponds to data unmodified by the de-randomizer circuit, and wherein a second portion of the soft data values corresponds to data modified by the de-randomizer circuit; and

a data decoder circuit operable to yield a decoded output from the soft data, wherein the soft data generation circuit and the data decoder circuit are hardware circuits.

2. The data storage system of claim 1 , wherein the data decoder circuit is operable to apply a soft decoding algorithm to the soft data to yield the decoded output.

3. The data storage system of claim 2 , wherein the soft decoding algorithm is a low density parity check decoding algorithm.

4. The data storage system of claim 1 , wherein each instance of the element is read using a different reference value.

5. The data storage system of claim 1 , wherein the solid state memory device comprises a single bit per cell flash memory.

6. The data storage system of claim 1 , wherein the solid state memory device comprises a multi-bit per cell flash memory, wherein the multiple instances of the element includes a first set of instances corresponding to a first bit in a cell of the multi-bit bit per cell flash memory, and a second set of instances of the element corresponds to a second bit in the cell of the multi-bit per cell flash memory.

7. The data storage system of claim 6 , wherein the scramble compensating extended look up table includes a first set of soft data values corresponding to different possible values for the first set of instances, and a second set of soft data values corresponding to different possible values for the second set of instances.

8. The data storage system of claim 7 , further comprising a data de-randomizer circuit operable to de-randomize the soft data, wherein a first portion of the first set of soft data values corresponds to data unmodified by the de-randomizer circuit, and wherein a second portion of the first set of soft data values corresponds to data modified by the de-randomizer circuit.

9. The data storage system of claim 8 , wherein all of the second portion of the first set of soft data values corresponds to data modified by the de-randomizer circuit.

10. The data storage system of claim 8 , wherein all of the second portion of the first set of soft data values corresponds to data unmodified by the de-randomizer circuit.

11. A method for recovering data from a solid state memory device, the method comprising:

accessing, via a soft data generation circuit, a cell of a solid state memory device to yield, in conjunction with a data decoder circuit, multiple instances of a read;

accessing, via the soft data generation circuit, a scramble compensating extended look up table using the multiple instances to receive corresponding soft data, wherein the soft data generation circuit and the data decoder circuit are hardware circuits; and

de-randomizing, via a data de-randomizer circuit, the soft data, wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element, wherein a first portion of the soft data values corresponds to data unmodified by the de-randomizer circuit, and wherein a second portion of the soft data values corresponds to data modified by the de-randomizer circuit.

12. The method of claim 11 , wherein accessing the cell includes repeatedly accessing the cell using different reference values.

13. The method of claim 11 , further comprising:

applying a de-randomizer algorithm using a de-randomizer circuit to each of the multiple instances of the read to yield corresponding de-randomized instances; and

accessing the scramble compensating extended look up table using the de-randomized instances.

14. The method of claim 11 , the method further comprising:

applying a low density parity check decoding algorithm to the soft data to yield a decoded output.

15. The method of claim 11 , wherein the solid state memory device is selected from a group consisting of: a single bit per cell flash memory, a multi-bit per cell flash memory configured to operate in a single bit per cell mode, and a lower page only mode of a multi-level flash memory.

16. The method of claim 11 , further comprising providing a de-randomizer circuit, wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element, wherein a first portion of the soft data values correspond to data unmodified by the de-randomizer circuit, and wherein a second portion of the soft data values correspond to data modified by the de-randomizer circuit.

17. The method of claim 11 , wherein the solid state memory device comprises a multi-bit per cell flash memory, wherein the multiple instances of the element includes a first set of instances corresponding to a first bit in a cell of the multi-bit per cell flash memory, and a second set of instances corresponding to a second bit in the cell of the multi-bit per cell flash memory.

18. A data storage system, the system comprising:

a memory device;

a soft data generation circuit operable to:

receive multiple instances of an element of a read data set accessed from the memory device; and

access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data;

a data de-randomizer circuit operable to de-randomize the soft data, wherein the scramble compensating extended look up table includes a number of soft data values corresponding to different possible values for the multiple instances of the element, wherein a first portion of the soft data values corresponds to data unmodified by the de-randomizer circuit, and wherein a second portion of the soft data values corresponds to data modified by the de-randomizer circuit; and

a data decoder circuit operable to yield a decoded output from the soft data, wherein the soft data generation circuit and the data decoder circuit are hardware circuits.