Semiconductor memory device that applies same voltage to two adjacent word lines for access
View Patent ↗A semiconductor memory device includes a block of memory cells including first, second, and third memory cells, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, and a control circuit configured to access the block in one of at least first and second modes to perform an operation thereon. When the control circuit accesses the block in the first mode, the same voltage is applied to the first and second word lines throughout the operation, and when the control circuit accesses the block in the second mode, the same voltage is applied to the second and third word lines throughout the operation.
1. A semiconductor memory device, comprising:
a block of memory cells including a first memory cell, a second memory cell, and a third memory cell;
a first word line electrically connected to a gate of the first memory cell;
a second word line extending adjacent to the first word line and electrically connected to a gate of the second memory cell;
a third word line extending adjacent to the second word line and electrically connected to a gate of the third memory cell;
a driver configured to supply voltages to the first, second, and third word lines; and
a control circuit coupled to the driver and configured to access the block in a normal mode, a first mode, and a second mode for performing an operation on the block, wherein
when the control circuit accesses the second memory cell of the block in the first mode, the control circuit causes the driver to supply a voltage to the first word line that is the same as a voltage supplied by the driver to the second word line throughout the operation being performed on the block, and
when the control circuit accesses the second memory cell of the block in the second mode, the control circuit causes the driver to supply a voltage to the second word line that is the same as a voltage supplied by the driver to the third word line throughout the operation being performed on the block, and
when the control circuit accesses the second memory cell of the block in the normal mode, the control circuit causes the driver to supply a voltage to the second word line that is different from a voltage supplied by the driver to the first word line and different from a voltage supplied to the third word line by the driver during at least a part of the operation being performed on the block,
the control circuit accesses the block in the normal mode in response to receiving a normal access command,
the control circuit accesses the block in the first mode in response to receiving a first access command that is directly followed by the normal access command, and
the control circuit accesses the block in the second mode in response to receiving a second access command that is directly followed by the normal access command.
2. The device according to claim 1 , wherein
the block of memory cells includes a memory string which includes the first, second, and third memory cells electrically connected in series, the first and second memory cells being adjacent memory cells in the memory string and the second and third memory cells being adjacent memory cells in the memory string.
3. The device according to claim 2 , wherein
the first, second, and third memory cells are stacked one above the other on a substrate.
4. The device according to claim 1 , further comprising:
a memory region storing a block table that indicates whether the block is to be accessed in the normal mode, the first mode, or the second mode.
5. The device according to claim 4 , wherein the block table further indicates whether or not the block is a bad block.
6. The device according to claim 1 , wherein
when the control circuit accesses the second memory cell of the block in the first mode, a voltage supplied to the third word line by the driver differs from a voltage supplied to the first and second word lines by the driver during the operation, and
when the control circuit accesses the second memory cell of the block in the second mode, a voltage supplied to the first word line by the driver is different from the voltage supplied to the second and third word lines by the driver, at least partially during the operation.
7. The device according to claim 1 , wherein the operation includes a read operation.
8. The device according to claim 1 , wherein the operation includes a write operation.
9. The device according to claim 8 , wherein
the first memory cell, the second memory cell, and the third memory cell are connected to a same bit line,
when the control circuit accesses the second memory cell of the block in the first mode, the same data are written in the first memory cell and the second memory cell, and
when the control circuit accesses the second memory cell of the block in the second mode, the same data are written in the second memory cell and the third memory cell.
10. The device according to claim 1 , wherein the operation includes an erase operation.
11. The device according to claim 1 , wherein
a data capacity of the block in the first mode and in the second mode is half a data capacity of the block in the normal mode.
12. The device according to claim 1 , wherein
the control circuit is further configured to carry out a first check operation to read data from predetermined memory cells of the block in the normal mode, and set an access mode of the block as the normal mode when data are successfully read from the predetermined memory cells during the first check operation.
13. The device according to claim 12 , wherein
the control circuit is further configured to carry out a second check operation to read data from the predetermined memory cells of the block in the first mode, and a third check operation to read data from the predetermined memory cells of the block in the second mode.
14. The device according to claim 13 , wherein
the control circuit sets the access mode of the block as the first mode, when data are not successfully read from the predetermined memory cells during the first check operation and the third check operation, and are successfully read from the predetermined memory cells during the second check operation.
15. The device according to claim 14 , wherein
the control circuit sets the access mode of the block as the second mode, when data are not successfully read from the predetermined memory cells during the first check operation and the second check operation, and are successfully read from the predetermined memory cells during the third check operation.
16. The device according to claim 15 , wherein
the control circuit sets the block as a bad block, when data are not successfully read from the predetermined memory cells during any one of the first check operation, the second check operation, and the third check operation.