Semiconductor memory device that applies an initial pass voltage followed by a final pass voltage to non-selected word lines during a write operation

1. A non-volatile semiconductor memory device comprising:

a first memory cell above a substrate and electrically connected to a first word line;

a second memory cell above the first memory cell and electrically connected to a second word line; and

a controller configured to execute a write operation that includes a first step, a second step after the first step, and a third step after the second step, wherein

in the first step, a first voltage is applied to the first word line and to a first non-selected word line when the first memory cell is being written, and a second voltage that is lower than the first voltage is applied to the second word line and to a second non-selected word line when the second memory cell is being written;

in the second step, a first program voltage is applied to the first word line when the first memory cell is being written, and a second program voltage is applied to the second word line when the second memory cell is being written;

in the third step, a third voltage higher than the first and second voltages is applied to the first non-selected word line when the first memory cell is being written and to the second non-selected word line when the second memory cell is being written; and

a time period between a start of the second step and a start of the third step is different depending on whether the first memory cell is being written or the second memory cell is being written.

2. The device according to claim 1 , wherein

the time period between the start of the second step and the start of the third step is longer when the second memory cell is being written than when the first memory cell is being written.

3. The device according to claim 1 , wherein the first program voltage and the second program voltage are the same.

4. The device according to claim 1 , wherein an overshoot of the voltage applied to the first or second non-selected word line in the first step occurs as a result of the program voltage being applied to the first or second word line in the second step, and the third step is started when the overshoot is stabilized.

5. The device according to claim 4 , wherein the time taken to stabilize the overshoot is shorter when the first memory cell is being written than when the second memory cell is being written.

6. The device according to claim 1 , further comprising a semiconductor pillar extending above substrate, wherein channel regions of the first and second memory cells are formed on the semiconductor pillar at different distances away from the substrate, the channel region of the first memory cell having a smaller cross-section area than the channel region of the second memory cell.

7. The device according to claim 1 , wherein the first non-selected word line is adjacent to the first word line and the second non-selected word line is adjacent to the second word line.

8. A non-volatile semiconductor memory device comprising:

a first memory cell above a substrate and electrically connected to a first word line;

a second memory cell above the first memory cell and electrically connected to a second word line; and

a controller configured to execute a write operation that includes a first step, a second step after the first step, and a third step after the second step, wherein

in the first step, a first voltage is applied to the first word line and to a first non-selected word line when the first memory cell is being written, and a second voltage that is different from the first voltage is applied to the second word line and to a second non-selected word line when the second memory cell is being written;

in the second step, a first program voltage is applied to the first word line when the first memory cell is being written, and a second program voltage is applied to the second word line when the second memory cell is being written; and

in the third step, a third voltage higher than the first and second voltages is applied to the first non-selected word line when the first memory cell is being written and a fourth voltage higher than the first and second voltages is applied to the second non-selected word line when the second memory cell is being written.

9. The device according to claim 8 , wherein the second voltage is lower than the first voltage.

10. The device according to claim 8 , wherein

the time period between the start of the second step and the start of the third step when the first memory cell is being written and the time period between the start of the second step and the start of the third step when the second memory cell is being written are substantially the same.

11. The device according to claim 8 , wherein

the time period between the start of the second step and the start of the third step is longer when the second memory cell is being written than when the first memory cell is being written.

12. The device according to claim 8 , wherein the third voltage and the fourth voltage are the same.

13. The device according to claim 8 , wherein the first program voltage and the second program voltage are the same.

14. The device according to claim 8 , further comprising a semiconductor pillar extending above substrate, wherein channel regions of the first and second memory cells are formed on the semiconductor pillar at different distances away from the substrate, the channel region of the first memory cell having a smaller cross-section area than the channel region of the second memory cell.

15. A method of performing a write operation in a non-volatile semiconductor memory device comprising a first memory cell above a substrate and electrically connected to a first word line and a second memory cell above the first memory cell and electrically connected to a second word line, the write operation including a first step, a second step after the first step, and a third step after the second step, said method comprising:

in the first step, applying a first voltage to the first word line and to a first non-selected word line when the first memory cell is being written and applying a second voltage that is different from the first voltage to the second word line and to a second non-selected word line when the second memory cell is being written;

in the second step, applying a first program voltage to the first word line when the first memory cell is being written and applying a second program voltage to the second word line when the second memory cell is being written; and

in the third step, applying a third voltage higher than the first and second voltages to the first non-selected word line when the first memory cell is being written and applying a fourth voltage higher than the first and second voltages to the second non-selected word line when the second memory cell is being written.

16. The method according to claim 15 , wherein the second voltage is lower than the first voltage.

17. The method according to claim 15 , wherein

the time period between the start of the second step and the start of the third step when the first memory cell is being written and the time period between the start of the second step and the start of the third step when the second memory cell is being written are substantially the same.

18. The method according to claim 15 , wherein

the time period between the start of the second step and the start of the third step is longer when the second memory cell is being written than when the first memory cell is being written.

19. The method according to claim 15 , wherein the third voltage and the fourth voltage are the same.

20. The method according to claim 15 , wherein the first program voltage and the second program voltage are the same.