Semiconductor memory device

1. A semiconductor memory device comprising:

a first block of memory cells including a first word line above a substrate, a second word line above the first word line, and a third word line above the second word line;

a first control gate line electrically connected to the first word line;

a second control gate line electrically connected to the second word line and between the first control gate line and the first block;

a third control gate line electrically connected to the third word line and between the second control gate line and the first block; and

a fourth control gate line between the second and third control gate lines and electrically connected to a fourth word line that is between the first and second word lines.

2. The device according to claim 1 , further comprising:

a fifth control gate line between the first and second control gate lines and electrically connected to a fifth word line that is between the first and fourth word lines.

3. The device according to claim 2 , wherein

the first through fifth word lines have different resistances, the third word line having the highest resistance and the fourth word line having the second highest resistance.

4. A semiconductor memory device comprising:

a first block of memory cells including a first word line above a substrate, a second word line above the first word line, and a third word line above the second word line;

a first control gate line electrically connected to the first word line;

a second control gate line electrically connected to the second word line and between the first control gate line and the first block;

a third control gate line electrically connected to the third word line and between the second control gate line and the first block; and

a fourth control gate line between the second and third control gate lines and electrically connected to a fourth word line that is above the third word line.

5. The device according to claim 4 , further comprising:

a fifth control gate line between the first and second control gate lines and electrically connected to a fifth word line that is between the first and second word lines.

6. The device according to claim 5 , wherein

the first through fifth word lines have different resistances, the third word line having the highest resistance and the fourth word line having the second highest resistance.

7. The device according to claim 1 , further comprising:

a first transfer transistor that is between the first word line and the first control gate line;

a second transfer transistor between the second word line and the second control gate line; and

a third transfer transistor between the third word line and the third control gate line.

8. A semiconductor memory device comprising:

a first block of memory cells including a first word line above a substrate, a second word line above the first word line, and a third word line above the second word line;

a first control gate line electrically connected to the first word line;

a second control gate line electrically connected to the second word line and between the first control gate line and the first block;

a third control gate line electrically connected to the third word line and between the second control gate line and the first block;

a second block of memory cells including a fourth word line electrically connected to the first word line and above the substrate, a fifth word line electrically connected to the second word line and above the fourth word line, and a sixth word line electrically connected to the third word line and above the fifth word line;

a fourth control gate line electrically connected to the fourth word line;

a fifth control gate line electrically connected to the fifth word line and between the fourth control gate line and the second block; and

a sixth control gate line electrically connected to the sixth word line and between the fifth control gate line and the second block.

9. A semiconductor memory device comprising:

a first block of memory cells including a first word line above a substrate, a second word line above the first word line, and a third word line above the second word line;

a first control gate line electrically connected to the first word line;

a second control gate line electrically connected to the second word line and between the first control gate line and the first block;

a third control gate line electrically connected to the third word line and between the second control gate line and the first block;

a fourth control gate line between the first and second control gate lines and electrically connected to a fourth word line that is between the first word line and the substrate;

a fifth control gate line between the second and third control gate lines and electrically connected to a fifth word line that is between the first and fourth word lines; and

a sixth control gate line between the third control gate line and the first block and electrically connected to a sixth word line that is between the first word line and the fifth word line.

10. The device according to claim 9 , further comprising:

a fifth control gate line between the first and second control gate lines and electrically connected to a fifth word line that is between the first and fourth word lines.

11. The device according to claim 10 , wherein

the first through fifth word lines have different resistances, the third word line having the highest resistance and the fourth word line having the second highest resistance.

12. A semiconductor memory device comprising:

a first block of memory cells including a first stack of word lines above a substrate;

a second block of memory cells including a second stack of word lines above the substrate;

a first set of control gate lines, each of which is electrically connected to one of the word lines of the second block;

a second set of control gate lines between the first set of control gate lines and the first and second blocks, each of the control gate lines of the second set being electrically connected to one of the word lines of the first block;

a third set of control gate lines, each of which is electrically connected to one of the word lines of the second block, wherein the first and second blocks are between the second and third sets of control gate lines; and

a fourth set of control gate lines, each of which is electrically connected to one of the word lines of the first block, wherein the third set of control gate lines is between the fourth set of control gate lines and the first and second blocks.

13. The device according to claim 12 , wherein

each of the word lines in the first stack is electrically connected to one of the word lines in the second stack.

14. The device according to claim 12 , wherein

the first stack of word lines includes a first word line above the substrate, a second word line above the first word line, and a third word line above the second word line; and

the second set of control gate lines includes a first control gate line electrically connected to the first word line, a second control gate line electrically connected to the second word line and between the first control gate line and the first and second blocks, and a third control gate line electrically connected to the third word line and between the second control gate line and the first and second blocks.

15. The device according to claim 14 , wherein the second set of control gate lines further comprises:

a fourth control gate line between the second and third control gate lines and electrically connected to a fourth word line that is between the first and second word lines; and

a fifth control gate line between the first and second control gate lines and electrically connected to a fifth word line that is between the first and fourth word lines.

16. The device according to claim 15 , wherein

the first through fifth word lines have different resistances, the third word line having the highest resistance and the fourth word line having the second highest resistance.

17. The device according to claim 14 , wherein the second set of control gate lines further comprises:

a fourth control gate line between the second and third control gate lines and electrically connected to a fourth word line that is above the third word line; and

a fifth control gate line between the first and second control gate lines and electrically connected to a fifth word line that is between the first and second word lines.

18. The device according to claim 17 , wherein

the first through fifth word lines have different resistances, the third word line having the highest resistance and the fourth word line having the second highest resistance.

19. The device according to claim 12 , wherein

each of the control gate lines is connected to one of the word lines through a transfer transistor.