Enhancement-depletion mode circuit element with differential passivation

1. An enhancement-depletion circuit element comprising:

a depletion-mode load transistor and an enhancement-mode drive transistor formed from the common elements of:

a first patterned conductive layer including a load gate electrode and a drive gate electrode;

a patterned inorganic dielectric stack including a load gate dielectric and a drive gate dielectric;

a patterned inorganic semiconductor layer including a load semiconductor region and a drive semiconductor region;

a second patterned conductive layer including a load source, a load drain, a drive source and a drive drain; and

a patterned differential passivation structure having a patterned polymer dielectric layer and a patterned conformal inorganic dielectric layer;

the depletion-mode load transistor having a load back-channel in contact with the patterned conformal inorganic dielectric layer; and

the enhancement-mode drive transistor having a drive back-channel in contact with the patterned polymer dielectric layer.

2. The element of claim 1 , wherein the load transistor and the drive transistor each have a planar bottom-gate architecture.

3. The element of claim 1 , wherein the load transistor and the drive transistor each have a vertical bottom-gate architecture.

4. The element of claim 3 , wherein the drive transistor is a first drive transistor, and further comprising a drive VTFT structure and a second drive transistor connected in series and sharing the drive gate with the first drive transistor, the second drive transistor having a vertical bottom-gate architecture, the first drive transistor and the second drive transistor being formed over the drive VTFT structure.

5. The element of claim 3 , wherein the load transistor is a first load transistor, and further comprising a load VTFT structure and a second load transistor connected in series and sharing the load gate with the first load transistor, the second load transistor having a vertical bottom-gate architecture, the first load transistor and the second load transistor being formed over the load VTFT structure.

6. The element of claim 1 , wherein the load transistor has a planar bottom-gate architecture and the drive transistor has a vertical bottom-gate architecture.

7. The element of claim 6 , wherein the drive transistor is a first drive transistor, and further comprising a drive VTFT structure and a second drive transistor connected in series and sharing the drive gate with the first drive transistor, the second drive transistor having a vertical bottom-gate architecture, the first drive transistor and the second drive transistor being formed over the drive VTFT structure.

8. The element of claim 1 , wherein a thickness of the load gate dielectric is greater than that of the drive gate dielectric.

9. The element of claim 1 , wherein the semiconductor layer is a ZnO based semiconductor.

10. The element of claim 1 , further comprising an additional patterned polymer dielectric layer.

11. The element of claim 1 , further comprising an additional patterned inorganic dielectric layer.