IP Library Granted Patent US 9,864,547
Granted Patent B2
US 9,864,547 · App. 15/056,238 · Granted Jan 9, 2018

Storage device and control method

Inventors: Takashi Ishiguro (Yokohama, JP); Hirokazu Morita (Yokohama, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0659G06F1/32G06F3/0625G06F3/0634G06F3/0679Y02B60/1246
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Quick Facts
Patent No.
US 9,864,547
App. No.
15/056,238
Granted
Jan 9, 2018
Kind
B2
Abstract

According to one embodiment, a storage device includes a processor which executes first processing, second processing and third processing. The second processing includes processing for relaying a command issued by a host device, and an execution result of the first processing corresponding to the. command, between the host device and the first processing. The third processing includes processing for causing the second processing to transition from a first state to a second state of lower energy consumption than the first state, when a first period in which the second processing is in an idle state exceeds a second period. The third processing further includes processing for maintaining the first state under a first condition, when the first period exceeds the second period.

Claims (33)

1. A storage device comprising:

a nonvolatile first memory;

a volatile second memory; and

a processor which communicates with a host device connected to the storage device via a communication path, wherein:

the processor executes first processing, second processing and third processing;

the first processing comprises processing for access to the first memory through the second memory;

the second processing comprises processing for relaying a command to request access to the first memory issued by the host device, and an execution result of the first processing corresponding to the command, between the host device and the first processing;

the third processing comprises processing for causing the second processing to transition from a first state to a second state of lower energy consumption than the first state, when a first period in which the second processing is in an idle state exceeds a second period; and

the third processing further comprises processing for maintaining the first state of the second processing under a first condition, when the first period exceeds the second period.

2. The storage device of claim 1 , wherein the third processing further comprises processing for causing the second processing to transition to the first state under a second condition, when the second processing is in the second state and when the second processing is in the idle state.

3. The storage device of claim 1 , wherein the first condition comprises a condition that an uncompleted command being processed by the first processing is present.

4. The storage device of claim 1 , wherein the first condition comprises a condition that a transmission length of an uncompleted command being processed by the first processing is less than a first value.

5. The storage device of claim 1 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the second processing is in the second state while the first processing corresponding to the command to request read of data from the first memory is being executed, and when the first memory completes preparation of the data which is an object to be read.

6. The storage device of claim 1 , wherein the third processing further comprises processing for causing the second processing to transition Lo the first state, when the second processing is in the second state while the first processing corresponding to the command to request read of data from the first memory is being executed, and when storing of data which is an object to be read and which is stored in the first memory in the second memory is completed.

7. The storage device of claim 1 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the second processing is in the second state while the first processing corresponding to the command to request access to the first memory is being executed, and when a third period elapsed from a time when an uncompleted command being processed by the first processing is relayed exceeds a fourth period longer than the second period.

8. The storage device of claim 7 , wherein the fourth period is determined based on the transmission length of the uncompleted command being processed by the first processing.

9. A storage device comprising:

a memory; and

a controller which controls a communication path used for communicating with a host device, wherein:

the controller causes the communication path to transition from a first state to a second state of lower energy consumption than the first state, when a first period exceeds a second period, the first period being a period in which communication for receiving a command issued by the host device to request access to the memory, and communication for returning an execution result of the command to the host device are in a non-execution state, and

the controller maintains the first state of the communication path under a first condition, when the first period exceeds the second period.

10. A control method for a storage device comprising a nonvolatile first memory and a volatile second memory, the method comprising:

executing first processing for access to the first memory through the intervention of the second memory;

executing second processing for relaying a command to request access to the first memory issued by a host device connected to the storage device via a communication path, and an execution result of the first processing corresponding to the command, between the host device and the first processing; and

executing third processing for causing the second processing to transition from a first state to a second state of lower energy consumption than the first state, when a first period in which the second processing is in an idle state exceeds a second period,

wherein the third processing comprises processing for maintaining the first state of the second processing under a first condition, when the first period exceeds the second period.

11. The control method of claim 10 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the communication path is in the second state and the second processing is in the idle state, under a second condition.

12. The control method of claim 10 , wherein the first condition comprises a condition that an uncompleted command being processed by the first processing is present.

13. The control method of claim 10 , wherein the first condition comprises a condition that a transmission length of an uncompleted command being processed by the first processing is less than a first value.

14. The control method of claim 10 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the second processing is in the second state while the first processing corresponding to the command to request read of data from the first memory is being executed, and when the first memory completes preparation of data which is an object to be read.

15. The control method of claim 10 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the second processing is in the second state while the first processing corresponding to the command to request read of data from the first memory is being executed, and when storing of data which is an object to be read and which is stored in the first memory in the second memory is completed.

16. The control method of claim 10 , wherein the third processing further comprises processing for causing the second processing to transition to the first state, when the second processing is in the second state while the first processing corresponding to the command to request access to the first memory is being executed, and when a third period elapsed from a time when an uncompleted command being processed by the first processing is relayed exceeds a fourth period longer than the second period.

17. The control method of claim 16 , wherein the fourth period is determined based on the transmission length of the uncompleted command being processed by the first processing.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0798 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2016
From: ISHIGURO, TAKASHI; MORITA, HIROKAZU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037852/0910 →
Priority Claims (1)
JP 2015-155918 · Aug 6, 2015 · national
Continuity (1)
Related Publication 20170038970A1 · Feb 9, 2017