Semiconductor device with improved reverse recovery characteristics
A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
1. A semiconductor device comprising a diode and a semiconductor substrate, wherein the diode comprises:
an anode electrode provided on a front surface of the semiconductor substrate;
a cathode electrode provided on a back surface of the semiconductor substrate;
a p-type anode region provided in the semiconductor substrate and connected to the anode electrode;
an n-type barrier region provided in the semiconductor substrate and in contact with the anode region from a back side of the anode region;
an n-type pillar region provided in the semiconductor substrate and connected to the anode electrode, the pillar region piercing through the anode region from the front surface of the semiconductor substrate and reaching the barrier region; and
an n-type cathode region provided in the semiconductor substrate, disposed on a back side of the barrier region, and connected to the cathode electrode,
wherein
a lifetime control layer is provided in an area within the cathode region, the area being located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate, the lifetime control layer having crystal defects which are distributed along a planar direction of the semiconductor substrate, and
a peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.
2. The semiconductor device according to claim 1 , wherein
a p-type separate region separating the barrier region and the cathode region is provided between the barrier region and the cathode region.
3. The semiconductor device according to claim 1 , further comprising an IGBT, wherein the IGBT comprises:
an emitter electrode provided on the front surface;
a collector electrode provided on the back surface;
n-type emitter region provided in the semiconductor substrate and connected to the emitter region;
a p-type body region provided in the semiconductor substrate and in contact with the emitter region from a back side of the emitter region;
an n-type IGBT drift region provided in the semiconductor substrate, disposed at a back side of the body region, connected to the cathode electrode, and separated from the emitter region by the body region;
a p-type collector region provided in the semiconductor substrate, in contact with the IGBT drift region from a back side of the IGBT drift region, connected to the collector electrode, and separated from the body region by the IGBT drift region; and
a gate electrode facing the body region via a gate insulating film in a range where the emitter region and the IGBT drift region are separated by the body region,
wherein
the lifetime control layer extends across the cathode region and the IGBT drift region.
4. The semiconductor device according to claim 1 , further comprising an IGBT, wherein
the IGBT comprises:
an emitter electrode provided on the front surface;
a collector electrode provided on the back surface;
an n-type emitter region provided in the semiconductor substrate and connected to the emitter region;
a p-type body region provided in the semiconductor substrate and in contact with the emitter region from a back side of the emitter region;
an n-type IGBT drift region provided in the semiconductor substrate, disposed at a back side of the body region, connected to the cathode electrode, and separated from the emitter region by the body region;
a p-type collector region provided in the semiconductor substrate, in contact with the IGBT drift region from a back side of the IGBT drift region, connected to the collector electrode, and separated from the body region by the IGBT drift region; and
a gate electrode facing the body region via a gate insulating film in a range where the emitter region and the IGBT drift region are separated by the body region,
wherein
the lifetime control layer extends across the cathode region and the IGBT drift region.