IP Library Granted Patent US 9,831,176
Granted Patent B2
US 9,831,176 · App. 15/059,112 · Granted Nov 28, 2017

Semiconductor integrated circuit device and method of manufacturing the same

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Quick Facts
Patent No.
US 9,831,176
App. No.
15/059,112
Granted
Nov 28, 2017
Kind
B2
Abstract

A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.

Claims (19)

1. A semiconductor integrated circuit device, comprising:

a semiconductor substrate;

an insulating film formed on the semiconductor substrate;

two conductors made of metal and disposed at a distance from each other on the insulating film;

a first high-melting point metal film layered on each of the two conductors; and

a fuse element made from an amorphous silicon layer, which extends continuously between the two conductors and on the insulating film where the two conductors are spaced apart from each other, and which covers a top surface of each first high-melting point metal film and side surfaces of the two conductors.

2. A semiconductor integrated circuit device according to claim 1 , wherein a second high-melting point metal film, which has the same shape in plan view as a shape of the amorphous silicon layer, is formed under the amorphous silicon layer.

3. A semiconductor integrated circuit device according to claim 1 ,

wherein the semiconductor integrated circuit device comprises at least two metal wiring layers,

wherein the two conductors comprise a last metal wiring layer, which is the highest layer out of the at least two metal wiring layers, and

wherein, a protective film is disposed above the last metal wiring layer.

4. A semiconductor integrated circuit device according to claim 3 ,

wherein the protective film comprises a silicon oxide film and a silicon nitride film formed above the silicon oxide film, and

wherein the silicon nitride film is removed from above the fuse element to form an opening.

5. A semiconductor integrated circuit device according to claim 1 , wherein the first high-melting point metal film comprises one of a TiN film and a Ti compound film.

6. A semiconductor integrated circuit device according to claim 2 , wherein the second high-melting point metal film comprises one of a TiN film and a Ti compound film.

7. A semiconductor integrated circuit device according to claim 1 , wherein the amorphous silicon layer has a thickness of 150 Å or more and 1,000 Å or less.

8. A semiconductor integrated circuit device according to claim 3 , wherein the last metal wiring layer is used for wiring in other portions of the semiconductor integrated circuit device than the fuse element, and for a bonding pad.

9. A semiconductor integrated circuit device according to claim 8 , wherein the semiconductor integrated circuit device comprises an anti-reflection film that is formed from one of a TiN film and a Ti compound film, and that is absent from a space above the last metal wiring layer.

Assignments (3)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2016
From: HARADA, HIROFUMI
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037879/0044 →