IP Library Granted Patent US 10,282,288
Granted Patent B2
US 10,282,288 · App. 15/059,785 · Granted May 7, 2019

Memory system and method for controlling nonvolatile memory

Inventor: Shinichi Kanno (Tokyo, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F12/0246G06F3/06G06F2212/1044G06F2212/7201G06F2212/7205
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,282,288
App. No.
15/059,785
Granted
May 7, 2019
Kind
B2
Abstract

According to one embodiment, a memory system includes a nonvolatile memory, and a controller electrically connected to the nonvolatile memory. The controller receives, from a host, a write command including a logical block address. The controller obtains a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to the logical block address to a current write to the logical block address, or time data associated with a time elapsing from the last write to the logical block address to the current write to the logical block address. The controller notifies the host of the total amount of data or the time data as a response to the received write command.

Claims (32)

1. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to

receive, from a host, a write command including a logical block address;

obtain a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to a logical block address identical with the logical block address included in the received write command to a current write to the logical block address included in the received write command, or time data representing a time elapsing from a time of the last write to the logical block address identical with the logical block address in the received write command to a time of the current write to the logical block address included in the received write command; and

notify the host of the total amount of data or the time data upon completion of the received write command.

2. The memory system of claim 1 , wherein the controller is configured to notify the host of the total amount of data or the time data as a permission response to the received write command.

3. The memory system of claim 1 , wherein the controller is configured to

obtain the total amount of data, based on a first physical storage position in the nonvolatile memory, in which data was written by the last write to the logical block address identical with the logical block address included in the received write command, a second physical storage position in the nonvolatile memory, in which data is to be written by the current write to the logical block address included in the received write command, and the number of blocks allocated for writing data from the host during a time ranging from allocation of a first block including the first physical storage position to allocation of a second block including the second physical storage position; and

notify the host of the obtained total amount of data as a response to the received write command.

4. The memory system of claim 3 , wherein the controller is configured to acquire, as the first physical storage position, a physical address mapped to the logical block address identical with the logical block address included in the received write command, with reference to a logical-to-physical address translation table used to manage mapping between logical block addresses and physical addresses.

5. The memory system of claim 3 , wherein the controller is configured to

allocate one of free blocks in the nonvolatile memory as a write target block to which data from the host is to be written;

sequentially write data, received from the host, to available pages of the write target block while updating a logical-to-physical address translation table used to manage mapping between logical block addresses and physical addresses;

allocate a new free block as the write target block when the write target block includes no more available pages;

allocate numbers to blocks each allocated as the write target block, the numbers indicating order of the allocation of said blocks each allocated as the write target block; and

calculate the number of blocks allocated for writing data from the host during the time ranging from the allocation of the first block to the allocation of the second block, based on a number allocated to the first block including the first physical storage position, and a number allocated to the second block including the second physical storage position.

6. The memory system of claim 1 , wherein the controller is configured to notify the host of the total amount of data or the time data as a command completion response to the received write command.

7. The memory system of claim 1 , wherein the time data indicates a time interval between the last write and the current write.

8. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to

receive, from a host, a write command including a logical block address;

obtain a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to a logical block address identical with the logical block address included in the received write command to a current write to the logical block address included in the received write command, based on a first physical storage position in the nonvolatile memory, in which data was written by the last write to the logical block address, a second physical storage position in the nonvolatile memory, in which data is to be written by the current write to the logical block address included in the received write command, and the number of blocks allocated for writing data from the host during a time ranging from allocation of a first block including the first physical storage position to allocation of a second block including the second physical storage position; and

notify the host of the obtained total amount of data as a response to the received write command.

9. A method of controlling a nonvolatile memory, the method comprising:

receiving, from a host, a write command including a logical block address;

obtaining a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to a logical block address identical with the logical block address included in the received write command to a current write to the logical block address included in the received write command, or time data representing a time elapsing from a time of the last write to the logical block address identical with the logical block address in the received write command to a time of the current write to the logical block address included in the received write command; and

notifying the host of the total amount of data or the time data upon completion of the received write command.

10. The control method of claim 9 , wherein the notifying includes notifying the host of the total amount of data or the time data as a permission response to the received write command.

11. The control method of claim 9 , wherein the obtaining includes obtaining the total amount of data, based on a first physical storage position in the nonvolatile memory, in which data was written by the last write to the logical block address identical with the logical block address included in the received write command, a second physical storage position in the nonvolatile memory, in which data is to be written by the current write to the logical block address included in the received write command, and the number of blocks allocated for writing data from the host during a time ranging from allocation of a first block including the first physical storage position to allocation of a second block including the second physical storage position; and

the notifying includes notifying the host of the obtained total amount of data as a response to the received write command.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0798 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2016
From: KANNO, SHINICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 037884/0422 →
Priority Claims (1)
JP 2015-242998 · Dec 14, 2015 · national
Continuity (1)
Related Publication 20170168951A1 · Jun 15, 2017
Cited By (1)
US 12,307,116