IP Library Granted Patent US 10,366,835
Granted Patent B2
US 10,366,835 · App. 15/059,984 · Granted Jul 30, 2019

Plated terminations

Inventors: Andrew P. Ritter (Simpsonville, SC); Robert H. Heistand, II (St. Johns, FL); John L. Galvagni (Hendersonville, NC); Sriram Dattaguru (Myrtle Beach, SC)
Assignee: AVX Corporation
H01G4/30C23C18/1651C23C18/1653C23C18/32C23C18/38C23C18/48C23C28/021C23C28/023C25D3/56C25D5/02C25D5/34C25D7/00H01C1/14H01C7/008H01C7/10H01C17/28H01F41/04H01G4/005H01G4/008H01G4/012H01G4/06H01G4/12H01G4/228H01G4/232H05K3/02H05K3/403H05K2201/09709Y10T29/417Y10T29/42Y10T29/43Y10T29/435Y10T29/49002Y10T29/49099Y10T29/49101
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Quick Facts
Patent No.
US 10,366,835
App. No.
15/059,984
Granted
Jul 30, 2019
Kind
B2
Abstract

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Claims (35)

1. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the plurality of the interior plates being exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the plurality of interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where the edges of the plurality of interior plates are exposed upon the first surface, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and

concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,

wherein each of the first layer of electrically-conductive first metal on the first surface and the first layer of electrically-conductive first metal on the second surface is not deposited on any of the additional surfaces which meet the first surface, and

wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

2. The method of claim 1 , wherein each of electrolessly plating the first layer of electrically-conductive first metal on the first surface and concurrently electrolessly plating the first layer of electrically-conductive first metal on the second surface comprises electrolessly depositing the electrically-conductive first metal by immersing the entire capacitor in a plating solution.

3. The method of claim 2 , wherein the electrically-conductive first metal includes at least in part copper (Cu).

4. The method of claim 2 , wherein the electrically-conductive first metal includes at least in part nickel (Ni).

5. The method of claim 2 , wherein the electrically-conductive first metal includes at least in part copper (Cu) in combination with nickel (Ni).

6. The method of claim 2 further comprising: plating on top of the electrolessly-deposited electrically-conductive first layer a second-metal layer of an electrically-conductive second metal.

7. The method of claim 6 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electroless plating.

8. The method of claim 6 , wherein the electrically-conductive second-metal includes at least in part nickel (Ni).

9. The method of claim 6 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electrolytic plating.

10. The method of claim 6 , further comprising: plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal.

11. The method of claim 10 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electroless plating.

12. The method of claim 10 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electrolytic plating.

13. The method of claim 10 , wherein the electrically-conductive third-metal includes at least in part tin (Sn) in combination with lead (Pb).

14. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the interior plates are exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the interior plates are exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where edges of the plurality of interior plates are exposed upon the first surface by immersing the entire capacitor in a plating solution, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and

concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where edges of the plurality of interior plates are exposed upon the second surface while the entire capacitor is immersed in the plating solution, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,

wherein each of the first layer of electrically-conductive first metal on the first surface and the second layer of electrically-conductive first metal on the second surface extends to a third surface and a fourth surface on top of at least two of the plurality of anchor tabs, and

wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

15. The method of claim 14 , wherein the electrically-conductive first metal includes at least in part copper (Cu).

16. The method of claim 14 , wherein the electrically-conductive first metal includes at least in part nickel (Ni).

17. The method of claim 14 , wherein the electrically-conductive first metal includes at least in part copper (Cu) in combination with nickel (Ni).

18. The method of claim 14 , further comprising:

plating a second layer of an electrically-conductive second metal on top of the first layer of electrically-conductive first metal that is on the first surface; and

plating a second layer of the electrically-conductive second metal on the first layer of electrically-conductive first metal on the second surface.

19. The method of claim 18 , wherein plating the second layer on top of the first layer on the first surface and plating the second layer on top of the first layer on the second surface each comprises electroless plating.

20. The method of claim 18 , wherein the electrically-conductive second-metal includes at least in part nickel (Ni).

21. The method of claim 18 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electrolytic plating.

22. The method of claim 18 , further comprising: plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal.

23. The method of claim 22 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electroless plating.

24. The method of claim 22 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electrolytic plating.

25. The method of claim 22 , wherein the electrically-conductive third-metal includes at least in part tin (Sn) in combination with lead (Pb).

Assignments (1)
CHANGE OF NAME Recorded Dec 22, 2021
From: AVX CORPORATION
To: KYOCERA AVX COMPONENTS CORPORATION
Reel/Frame 058563/0762 →
Continuity (4)
Continuation 10951972 · Sep 28, 2004
Division 10409023 · Apr 8, 2003
Provisional Application 60372673 · Apr 15, 2002
Related Publication 20160189864A1 · Jun 30, 2016
Cited By (2)
US 12,580,126 US 12,614,677