IP Library Granted Patent US 10,353,599
Granted Patent B2
US 10,353,599 · App. 15/060,544 · Granted Jul 16, 2019

Storage system that has a plurality of managers among which a master manager is switchable

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Quick Facts
Patent No.
US 10,353,599
App. No.
15/060,544
Granted
Jul 16, 2019
Kind
B2
Abstract

A storage system includes a first storage unit including a first processor and a first array of node modules, each including a memory unit, and a second storage unit including a second processor and a second array of node modules, each including a memory unit. The first processor is configured to control the first and second storage units, and the second processor is configured to control the second storage unit and not the first storage unit when the first processor is set to control the first and second storage units, and control the first and second storage units, when the first processor is set to not control the second storage unit.

Claims (36)

1. A storage system, comprising:

a first storage unit including a first processor and a first array of node modules forming a grid arrangement in a first direction and a second direction that intersects the first direction, each node module including a memory chip and a node controller, the node controller being configured to transfer a packet including data to and from a node module in the first array adjacent in the first direction and a node module in the first array adjacent in the second direction, the packet having a first node address in the first direction and a second node address in the second direction; and

a second storage unit including a second processor and a second array of node modules forming a grid arrangement in a third direction and a fourth direction that intersects the third direction, each node module including a memory chip and a node controller, the node controller being configured to transfer a packet including data to and from a node module in the second array adjacent in the third direction and a node module in the second array adjacent in the fourth direction, wherein

the first processor is configured to control the first and second storage units, and

the second processor is configured to:

determine whether or not the first processor is set to control the second storage unit, using i) a first inquiry signal transmitted from the second processor to the first processor through a first communication path that includes the first and second arrays of node modules; and ii) a response to a second inquiry signal transmitted from the second processor to the first processor through a second communication path that does not include the first and second arrays of node modules,

control the second storage unit and not the first storage unit, when the first processor is set to control the first and second storage units, and

control the first and second storage units, when the first processor is set to not control the second storage unit.

2. The storage system according to claim 1 , wherein

the second processor determines whether or not the first processor is set to control the second storage unit, based on whether or not the first processor returns a response signal in response to the first inquiry signal.

3. The storage system according to claim 1 , wherein the first inquiry signal is periodically transmitted from the second processor to the first processor.

4. The storage system according to claim 1 , wherein

when the storage system begins operating in a state in which the second processor is set to control the first and second storage units, the first processor transmits priority data to the second processor, and the second processor changes a setting thereof so as not to control the first processor, if a priority set for the second storage unit is of a lower priority than that indicated by the priority data received from the first processor.

5. The storage system according to claim 1 , wherein

when the storage system is operating in a state in which the second processor is set to control the first and second storage units and the first processor is restored to an operating state, the first processor transmits priority data to the second processor, and the second processor transmits to the first processor, a signal indicating that the second processor will control the first and second storage units, in response to the priority data received from the first processor.

6. The storage system according to claim 1 , wherein

at least one of the first and second storage units includes a memory region storing a record of communications performed when the first processor controls the second storage unit and communications performed when the second processor controls the first storage unit.

7. The storage system according to claim 1 , further comprising:

a switch between the first processor and the second processor, that stores a record of communications performed when the first processor controls the second storage unit and communications performed when the second processor controls the first storage unit.

8. A method for controlling a storage system that has a first storage unit including a first processor and a first array of node modules, each including a memory unit; and a second storage unit including a second processor and a second array of node modules, each including a memory unit, the method comprising:

transmitting a first inquiry signal from the second processor to the first processor through a first communication path that includes the first and second arrays of node modules;

determining, by the second processor, whether or not the first processor is set to control the second storage unit based on a response to the first inquiry signal;

transmitting a second inquiry signal from the second processor to the first processor through a second communication path that does not include the first and second arrays of node modules;

determining, by the second processor, whether or not the first processor is set to control the second storage unit based also on a response to the second inquiry signal;

controlling the second storage unit and not the first storage unit, by the second processor, when the first processor is set to control the first and second storage units; and

controlling the first and second storage units, by the second processor, when the first processor is set to not control the second storage unit.

9. The method according to claim 8 , wherein

the second processor determines whether or not the first processor is set to control the second storage unit, based on whether or not the first processor returns the response.

10. The method according to claim 8 , wherein

the first inquiry signal is periodically transmitted from the second processor to the first processor.

11. The method according to claim 8 , further comprising:

transmitting priority data from the first processor to the second processor, when the storage system begins operating in a state in which the second processor is set to control the first and second storage units; and

changing a setting of the second processor so that the second processor does not control the first processor, if a priority set for the second storage unit is of a lower priority than that indicated by the priority data received from the first processor.

12. The method according to claim 8 , further comprising:

transmitting priority data from the first processor to the second processor, when the storage system is operating in a state in which the second processor is set to control the first and second storage units and the first processor is restored to an operating state; and

transmitting from the second processor to the first processor, a signal indicating that the second processor will control the first and second storage units, in response to the priority data.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2016
From: MANABE, SHINICHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038540/0567 →