Memory device that updates parameters transmitted to a host based on operational settings
View Patent ↗A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.
1. A memory device, comprising:
a semiconductor memory unit; and
a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit through a NAND interface circuit in response to commands received through the serial interface, and including a first register in which parameters of the memory device are stored, wherein
the controller circuit, in response to a host command to read parameters of the memory device, updates at least one of the parameters of the memory device stored in the first register based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host, and
the controller circuit includes an error-correcting code (ECG) circuit configured to perform error correction processes, one of the operational settings including an ECC setting either to enable the ECC circuit to perform the error correction processes or to disable the ECC circuit when the host performs the error correction processes, the parameters of the memory device stored in the first register including an error-bit parameter that indicates a number of error bits to be corrected by the host, wherein
the controller circuit, in response to a host command to read the error-bit parameter, updates the number of error bits to be corrected by the host, based on the ECC setting, such that when the number of error bits to be corrected by the host is zero and the ECC circuit is in a disabled state in accordance with the ECC setting, the number of error bits to be corrected by the host is updated to a number greater than zero.
2. The memory device according to claim 1 , wherein
the parameters of the memory device stored in the first register are factory-set parameters and are unchangeable.
3. The memory device according to claim 2 , wherein
the controller circuit, in response to a host command to change one or more of the operational settings, changes the operational settings in accordance with the host command.
4. The memory device according to claim 1 , wherein
the semiconductor memory unit logically divided into a plurality of pages,
the parameters of the memory device stored in the first register include a page-size parameter indicating a page size of each of the pages, and
the controller circuit, in response to a host command to read the page-size parameter, updates the page-size parameter based on the ECC setting.
5. The memory device according to claim 4 , wherein
when the ECC circuit is in a disabled state in accordance with the ECC setting, the page-size parameter is increased to a larger size.
6. The memory device according to claim 1 , wherein
the parameters of the memory device are stored in the semiconductor memory unit, and loaded into the first register from the semiconductor memory unit.
7. The memory device according to claim 1 , wherein the serial interface conforms to Serial Peripheral Interface (SPI).
8. The memory device according to claim 1 , wherein
the controller circuit includes a second register in which operational settings of the memory device are stored.
9. A method for communicating a parameter of a memory device from the memory device to a host through a serial interface, the memory device including a controller, an error-correcting code (ECC) circuit configured to perform error correction processes, and a semiconductor memory unit, the controller including a first register and a second register and accessing the semiconductor memory unit through a NAND interface circuit, the method comprising:
storing operational settings of the memory device in the first register, wherein one of the operational settings is an ECC setting to enable the ECC circuit to perform the error correction processes and to disable the ECC circuit when the host performs the error correction processes; and
in response to a host command to read parameters of the memory device, updating at least one of the parameters of the memory device stored in the second register based on the operational settings, and transmitting the updated parameters through the serial interface to the host, wherein
the parameters of the memory device stored in the second register include an error-bit parameter that indicates a number of error bits to be corrected by the host, and in response to a host command to read the error-bit parameter, the number of error bits to be corrected by the host is updated based on the ECC setting, such that when the number of error bits to be corrected by the host is zero and the ECC circuit is in a disabled state in accordance with the ECC setting, the number of error bits to be corrected by the host is updated to a number greater than zero.
10. The method according to claim 9 , wherein
the parameters of the memory device stored in the second register are factory-set parameters and are unchangeable.
11. The method according to claim 10 , wherein
in response to a host command to change one or more of the operational settings, changing the operational settings in accordance with the host command.
12. The method according to claim 9 , wherein
the memory device include a semiconductor memory unit logically divided into a plurality of pages,
the parameters of the memory device stored in the second register include a page-size parameter indicating a page size of each of the pages, and
in response to a host command to read the page-size parameter, the page-size parameter is updated based on the ECC setting.
13. The method according to claim 12 , wherein
when the ECC circuit is in a disabled state in accordance with the ECC setting, the page-size parameter is increased to a larger size.
14. A method for communicating a parameter of a memory device from the memory device to a host through a serial interface, the memory device including a controller and a semiconductor memory unit, the controller including a first register and a second register and accessing the semiconductor memory unit through a NAND interface circuit, the method comprising:
storing operational settings of the memory device in the first register, wherein one of the operational settings is an information indicating whether or not a block protection function in the semiconductor memory unit is valid; and
in response to a host command to read parameters of the memory device updating at least one of the parameters of the memory device stored in the second register based on the operational settings, and transmitting the updated parameters through the serial interface to the host, wherein
the parameters of the memory device stored in the second register are factory-set parameters and are unchangeable, and
in response to a host command to change one or more of the operational settings, changing the operational settings in accordance with the host command.