Memory device that performs an advance reading operation
View Patent ↗A memory device includes a semiconductor memory unit, and a controller configured to communicate with a host through a serial interface and access the memory semiconductor unit in response to commands received through the serial interface. The controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.
1. A memory device, comprising:
a semiconductor memory unit; and
a controller configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface, wherein
the controller, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.
2. The memory device according to claim 1 , wherein the controller determines a page that is designated in a non-read command received through the serial interface directly after the first read command as the second page.
3. The memory device according to claim 1 , wherein the controller includes first and second buffers, the data read from the first page being stored in the first buffer and the data read from the second page being stored in the second buffer.
4. The memory device according to claim 1 , wherein the controller issues the second command to the semiconductor memory unit, while sending through the serial interface the data that have been read from the first page in response to the first command.
5. The memory device according to claim 4 , wherein the controller includes first and second buffers, the data read from the first page being stored in the first buffer and the data read from the second page being stored in the second buffer.
6. The memory device according to claim 1 , wherein
the serial interface conforms to Serial Peripheral Interface (SPI).
7. A memory device, comprising:
a semiconductor memory unit; and
a controller configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface in a plurality of operational states including first and second operational states, wherein
the controller, in the first operational state, in response to a first read command received through the serial interface to read data in a first page of the semiconductor memory unit, issues a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command, and
the controller, in the second operational state, in response to the first read command received through the serial interface, issues the first command to the semiconductor memory unit to read data in the first page and does not issue the second command to read data in the second page.
8. The memory device according to claim 7 , wherein the controller, in the second operational state, determines a page that is designated in a non-read command received through the serial interface directly after the first read command as the second page.
9. The memory device according to claim 7 , wherein the controller, in the second operational state, issues the second command to the semiconductor memory unit, while sending through the serial interface the data that have been read from the first page in response to the first command.
10. The memory device according to claim 9 , wherein the controller includes first and second buffers, the data read from the first page being stored in the first buffer and the data read from the second page being stored in the second buffer.
11. The memory device according to claim 7 , wherein
the operational state of the controller is set based on a command received through the serial interface.
12. The memory device according to claim 11 , wherein
when the memory device is powered on, the controller initially operates in the first operational state.
13. The memory device according to claim 7 , wherein
the serial interface conforms to Serial Peripheral Interface (SPI).
14. A method for accessing a semiconductor memory unit of a memory device, comprising:
receiving, from a host through a serial interface, a first read command to read data in a first page of the semiconductor memory unit; and
in response to the first read command, issuing a first command to the semiconductor memory unit to read data in the first page and, in addition, a second command to read data in a second page that is consecutive to the first page and not specified in the first read command.
15. The method according to claim 14 , further comprising:
receiving, from the host through the serial interface, a non-read command that designates the second page.
16. The method according to claim 14 , wherein the second command is issued to the semiconductor memory unit, while the data that have been read from the first page in response to the first command are sent through the serial interface.
17. The method according to claim 14 , further comprising:
receiving, from the host through the serial interface, a second read command to read data in the second page of the semiconductor memory unit, wherein
at least part of the data in the second page has already been read from the semiconductor memory unit, when the second read command is received.