IP Library Granted Patent US 10,095,423
Granted Patent B2
US 10,095,423 · App. 15/063,203 · Granted Oct 9, 2018

Storage system that tracks mapping to a memory module to be detached therefrom

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Quick Facts
Patent No.
US 10,095,423
App. No.
15/063,203
Granted
Oct 9, 2018
Kind
B2
Abstract

A storage system connectable to a host includes a plurality of interface units, a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units, and a controller configured to maintain an address conversion table indicating mappings between logical addresses and physical addresses of memory locations in the semiconductor memory modules. When the controller determines that a first semiconductor memory module needs to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the corresponding logical addresses to another semiconductor memory module and update the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data.

Claims (28)

1. A storage system connectable to a host, comprising:

a plurality of interface units;

a plurality of semiconductor memory modules, each being detachably coupled with one of the interface units; and

a controller configured to maintain an address conversion table indicating mapping between a logical address and a physical address of a memory region of the semiconductor memory modules, wherein

when the controller determines that a first semiconductor memory module is to be detached, the controller converts physical addresses of the first semiconductor memory module into corresponding logical addresses using the address conversion table and copies valid data stored in the physical addresses to another semiconductor memory module and updates the address conversion table to indicate new mappings for the corresponding logical addresses of the valid data, and

after the first semiconductor memory module has been detached from the corresponding interface unit, the controller is further configured to stop data writing to remaining semiconductor memory modules when an over-provisioning ratio is smaller than a predetermined value.

2. The storage system according to claim 1 , wherein

after the first semiconductor memory module has been detached from the corresponding interface unit, the controller is further configured to invalidate data stored in at least one of the remaining semiconductor memory modules when the over-provisioning ratio is smaller than the predetermined value.

3. A method for tracking mappings between logical addresses and physical addresses of memory regions of a plurality of semiconductor memory modules that are detachably coupled with interface units of a storage system, the method comprising:

determining that a first semiconductor memory module is to be detached;

converting physical addresses of the first semiconductor memory module into corresponding logical addresses using the mappings;

copying valid data stored in the corresponding logical addresses of the first semiconductor memory module to another semiconductor memory module and updating the mappings to indicate new mappings for the corresponding logical addresses of the valid data; and

after the first semiconductor memory module has been detached from the corresponding interface unit, invalidating data stored in at least one of the remaining semiconductor memory modules when an over-provisioning ratio is smaller than a predetermined value.

4. The method according to claim 3 , further comprising:

sending the corresponding logical addresses to a host connected to the storage system.

5. The method according to claim 3 , wherein

the plurality of the semiconductor memory modules includes a plurality of physical blocks, each having a plurality of physical addresses, and is divided logically into a plurality of logical blocks, each logically containing a plurality of physical blocks of different semiconductor memory modules, and

in each of the logical blocks, user data and redundancy data are stored in different parts of the physical blocks.

6. The method according to claim 5 , further comprising:

when a read request of user data stored in a physical block of the first semiconductor memory module is received, after the first semiconductor memory module has been detached from the corresponding interface unit, restoring the requested user data using the redundancy data stored in physical blocks of the same logical block.

7. The method according to claim 6 , further comprising:

carrying out garbage collection with respect to each logical block that logically contains a physical block of the detached first semiconductor memory module.

8. The method according to claim 7 , wherein

a physical block that has not been mapped in an address conversion table is newly associated with and logically contained in the logical block that has been subjected to the garbage collection.

9. The method according to claim 5 , wherein

when the first semiconductor memory module is detached from the corresponding interface unit and a second semiconductor memory module is attached to said interface unit, a physical block of the second semiconductor memory module is newly associated with and logically contained in a logical block that logically contains a physical block of the first semiconductor memory module.

10. The method according to claim 3 , further comprising:

after the first semiconductor memory module has been detached from the corresponding interface unit, stopping data writing to remaining semiconductor memory modules when the over-provisioning ratio is smaller than the predetermined value.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2016
From: FUKUTOMI, KAZUHIRO; TANAKA, SHINGO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038621/0383 →