Patch panel for QSFP+ cable

1. A patch panel, comprising:

a circuit board;

a plurality of pairs of QSFP+ sockets connected to one another via conductive traces of the circuit board; and

one or more microcontrollers coupled to at least two of the conductive traces of each pair of QSFP+ sockets, wherein the one or more microcontrollers comprise memory storing instructions that when executed cause the one or more microcontrollers to perform operations comprising:

obtaining configuration settings for the QSFP+ sockets;

configuring connections of the QSFP+ sockets based on the configuration settings;

writing a value to a memory address of a given QSFP+ transceiver;

more than one day after writing the value, reading the value from the memory address; and

determining, based on the read value, an amount of usage.

2. The patch panel of claim 1 , comprising a data connection between the one or more microcontrollers and the QSFP+ sockets that consists essentially of:

a serial data line; and

a serial clock line, wherein the serial data line and serial clock line constitute a bus configured for multiple master devices and multiple slave devices.

3. The patch panel of claim 1 , wherein the operations comprise of:

obtaining temperature of a given QSFP+ transceiver;

comparing the obtained temperature to a threshold temperature value to determining whether the obtained temperature is above the threshold temperature value; and

in response to determining that the threshold temperature value is exceeded, emitting or logging an alarm.

4. The patch panel of claim 1 , the operations comprising:

obtaining a first configuration setting; and

configuring at least one of the QSFP+ sockets for a 1 by 40 gigabit per second connection based on the first configuration setting.

5. The patch panel of claim 4 , the operations comprising:

obtaining a second configuration setting; and

configuring at least one of the QSFP+ sockets for a 4×10 gigabit per second connection based on the second configuration setting.

6. The patch panel of claim 1 , wherein the configuration settings are received from a rack controller.

7. The patch panel of claim 1 , wherein the configuration settings are received from one or more jumpers.

8. The patch panel of claim 1 , wherein the operations comprise:

reading a sensor metric from a register of a given QSFP+ transceiver;

storing the sensor reading in a different address of memory of the QSFP+ transceiver;

more than one day after storing the sensor reading, reading the sensor metric from the different address and comparing to a current value of the register to determine whether a difference between the readings exceeds a threshold; and

in response to determining that the threshold is exceeded, emitting or logging an alarm.

9. The patch panel of claim 1 , wherein the one or more microcontrollers are configured to predict a fault indicating a failure of a component, and generate an alert responsive the predicted fault.

10. The patch panel of claim 1 , the operations comprising:

detecting a fault, the fault indicating a failure of a component; and

in response to detecting the fault, sending a message to a rack controller indicating a location of the failed component.

11. The patch panel of claim 1 , the operations comprising:

reading QSFP+ transceiver identifiers from memory; and

sending data indicative of a patch panel graph based on the transceiver identifiers indicating connections implemented by the patch panel.

12. The patch panel of claim 1 , comprising:

a rack comprising:

a plurality of computing devices connected via the patch panel, the plurality of computing devices storing in memory an operating system and an application.

13. The patch panel of claim 1 , comprising:

a first microcontroller coupled to a first pair of QSFP+ sockets; and

a second microcontroller coupled to a second pair of QSFP+ sockets.

14. The patch panel of claim 1 , the operations comprising:

reading a value indicative of transceiver temperature from a register of an EEPROM associated with a QSFP+ socket; and

based on the value, sending a signal to a rack controller that causes the rack controller to adjust a fan speed.

15. The patch panel of claim 1 , wherein the operations comprising:

periodically incrementing or decrementing a value in memory of the QSFP+ sockets to indicate usage.

16. The patch panel of claim 1 , comprising at least 8 pairs of QSFP+ sockets arrayed in spaced relation.

17. The patch panel of claim 1 , wherein the patch panel is configured to fit in N 19-inch U's of a rack, where N is an integer.

18. The patch panel of claim 1 , the operations comprising:

performing steps for monitoring a transceiver associated with one of the QFSP+ sockets.

19. The patch panel of claim 1 , the operations comprising:

reading, at a first time, a register of a transceiver associated with one of the QFSP+ sockets to obtain a first value, the register storing a value indicative of laser bias;

reading, at a second time after the first time, the register of the transceiver to obtain a second value;

determining a difference between the first value and the second value to determine a drift in laser bias; and

determining that the drift exceeds a threshold and, in response, emitting or logging an alarm.

20. A patch panel, comprising:

a circuit board;

a plurality of pairs of QSFP+ sockets connected to one another via conductive traces of the circuit board;

a data connection between the one or more microcontrollers and the QSFP+ sockets that consists essentially of:

a serial data line; and

a serial clock line, wherein the serial data line and serial clock line constitute a bus configured for multiple master devices and multiple slave devices; and

one or more microcontrollers coupled to at least two of the conductive traces of each pair of QSFP+ sockets, wherein the one or more microcontrollers comprise memory storing instructions that when executed cause the one or more microcontrollers to perform operations comprising:

obtaining configuration settings for the QSFP+ sockets; and

configuring connections of the QSFP+ sockets based on the configuration settings.

21. A patch panel, comprising:

a circuit board;

a plurality of pairs of QSFP+ sockets connected to one another via conductive traces of the circuit board; and

one or more microcontrollers coupled to at least two of the conductive traces of each pair of QSFP+ sockets, wherein the one or more microcontrollers comprise memory storing instructions that when executed cause the one or more microcontrollers to perform operations comprising:

obtaining configuration settings for the QSFP+ sockets;

configuring connections of the QSFP+ sockets based on the configuration settings;

reading a sensor metric from a register of a given QSFP+ transceiver;

storing the sensor reading in a different address of memory of the QSFP+ transceiver;

more than one day after storing the sensor reading, reading the sensor metric from the different address and comparing to a current value of the register to determine whether a difference between the readings exceeds a threshold; and

in response to determining that the threshold is exceeded, emitting or logging an alarm.

22. A patch panel, comprising:

a circuit board;

a plurality of pairs of QSFP+ sockets connected to one another via conductive traces of the circuit board; and

one or more microcontrollers coupled to at least two of the conductive traces of each pair of QSFP+ sockets, wherein the one or more microcontrollers comprise memory storing instructions that when executed cause the one or more microcontrollers to perform operations comprising:

obtaining configuration settings for the QSFP+ sockets;

configuring connections of the QSFP+ sockets based on the configuration settings; and

periodically incrementing or decrementing a value in memory of the QSFP+ sockets to indicate usage.

23. A patch panel, comprising:

a circuit board;

a plurality of pairs of QSFP+ sockets connected to one another via conductive traces of the circuit board; and

one or more microcontrollers coupled to at least two of the conductive traces of each pair of QSFP+ sockets, wherein the one or more microcontrollers comprise memory storing instructions that when executed cause the one or more microcontrollers to perform operations comprising:

obtaining configuration settings for the QSFP+ sockets;

configuring connections of the QSFP+ sockets based on the configuration settings;

reading, at a first time, a register of a transceiver associated with one of the QFSP+ sockets to obtain a first value, the register storing a value indicative of laser bias;

reading, at a second time after the first time, the register of the transceiver to obtain a second value;

determining a difference between the first value and the second value to determine a drift in laser bias; and

determining that the drift exceeds a threshold and, in response, emitting or logging an alarm.