Memory system and method of controlling nonvolatile memory
View Patent ↗According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller reads data from third memory cells included in the second memory cells by using the calculated second read voltage.
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks, the block including a plurality of physical sectors, the physical sector including memory cells connected to a word line; and
a controller configured to control the nonvolatile memory on a basis of a processing unit among a plurality of processing units, and configured to:
perform a distribution read on a first processing unit, the distribution read including searching a threshold voltage distribution of first memory cells corresponding to the first processing unit by reading data from the first memory cells a plurality of times with a different read voltage in each time, and acquire a first read voltage based on the searched threshold voltage distribution;
calculate a second read voltage based on the acquired first read voltage and a first relation, the second read voltage being a read voltage for second memory cells corresponding to a second processing unit, the first relation including a deviation amount between a threshold voltage distribution of the first processing unit and a threshold voltage distribution of the second processing unit, the second processing unit being a processing unit different from the first processing unit; and
read data from third memory cell among the second memory cells by using the calculated second read voltage.
2. The memory system according to claim 1 , wherein, in a case where an error correction process of the data read from the third memory cell fails, the controller determines whether or not the first read voltage is acquired and performs the distribution read on the first processing unit in a case where the first read voltage is not acquired.
3. The memory system according to claim 1 , wherein, in a case where an error correction process of the data read from the third memory cells fails, the controller determines whether or not the first read voltage is acquired and calculates the second read voltage by using the acquired first read voltage instead of performing the distribution read on the first processing unit in a case where the first read voltage is acquired.
4. The memory system according to claim 2 , wherein, in a case where an error correction process of the data read from the third memory cell using the second read voltage fails, the controller performs the distribution read on the second processing unit, and acquires a third read voltage, and re-reads data from the third memory cell by using the acquired third read voltage.
5. The memory system according to claim 1 , wherein the processing unit is a block, and the plurality of processing units are a plurality of the blocks, which are associated with a logical block, capable of executing parallel operations.
6. The memory system according to claim 1 , wherein the processing unit is a block, and the plurality of processing units are a plurality of blocks of which data is written during a same period.
7. The memory system according to claim 1 , wherein the processing unit is a physical sector, and the plurality of processing units are a plurality of physical sectors included in a same block.
8. The memory system according to claim 1 , wherein the nonvolatile memory has a two-dimensional structure.
9. The memory system according to claim 1 , wherein the nonvolatile memory has a three-dimensional structure, and the plurality of physical sectors are arranged in mutually-different layers.
10. The memory system according to claim 9 , wherein the first relation includes a deviation amount between a threshold voltage distribution of memory cells of a first layer in which first physical sectors are arranged and a threshold voltage distribution of memory cells of a second layer in which second physical sectors are arranged.
11. A method of controlling a nonvolatile memory, the nonvolatile memory including a plurality of blocks, the block including a plurality of physical sectors, the physical sector including memory cells connected to a same word line, the method comprising:
controlling the nonvolatile memory on a basis of a processing unit among a plurality of processing units,
performing, using circuitry, a distribution read on a first processing unit, the distribution read including searching a threshold voltage distribution of first memory cells corresponding to the first processing unit by reading data from the first memory cells a plurality of times with a different read voltage in each time, and acquiring a first read voltage based on the searched threshold voltage distribution;
calculating, using the circuitry, a second read voltage based on the acquired first read voltage and a first relation, the second read voltage being a read voltage for second memory cells corresponding to a second processing unit, the first relation including a deviation amount between a threshold voltage distribution of the first processing unit and a threshold voltage distribution of the second processing unit, the second processing unit being a processing unit different from the first processing unit; and
reading data from third memory cell among the second memory cells by using the calculated second read voltage.
12. The method according to claim 11 , further comprising, in a case where an error correction process of the data read from the third memory cell fails, determining whether or not the first read voltage is acquired and performing the distribution read on the first processing unit in a case where the first read voltage is not acquired.
13. The method according to claim 11 , further comprising, in a case where an error correction process of the data read from the third memory cell fails, determining whether or not the first read voltage is acquired and calculating the second read voltage by using the acquired first read voltage instead of performing the distribution read on the first processing unit in a case where the first read voltage is acquired.
14. The method according to claim 12 , further comprising, in a case where an error correction process of the data read from the third memory cell using the second read voltage fails, performing the distribution read on the second processing unit, acquiring a third read voltage, and re-reading data from the third memory cell by using the acquired third read voltage.
15. The method according to claim 11 , wherein the processing unit is a block, and the plurality of processing units are a plurality of the blocks, which are associated with a logical block, capable of executing parallel operations.
16. The method according to claim 11 , wherein the processing unit is a block, and the plurality of processing units are a plurality of blocks of which data is written during a same period.
17. The method according to claim 11 , wherein the processing unit is a physical sector, and the plurality of processing units are a plurality of physical sectors included in a same block.
18. The method according to claim 11 , wherein the nonvolatile memory has a two-dimensional structure.
19. The method according to claim 11 , wherein the nonvolatile memory has a three-dimensional structure, and the plurality of physical sectors are arranged in mutually-different layers.
20. The method according to claim 19 , wherein the first relation includes a deviation amount between a threshold voltage distribution of memory cells of a first layer in which first physical sectors are arranged and a threshold voltage distribution of memory cells of a second layer in which second physical sectors are arranged.