Memory device

1. A memory device comprising:

a memory cell which transitions to a first state or a second state by a first current flowing in the memory cell; and

a first circuit configured to stop supplying the first current when a first number of cycles of a clock signal lapses from reception of write data, the clock signal being input from outside the memory device;

wherein the first circuit comprises:

a first register configured to store a signal received at an input of the first circuit in response to a storing instruction, and output the stored signal in response to an output instruction,

a pulse generator configured to negate a first signal based on a signal being output from the first register, and

a write circuit configured to stop supplying the first current by the first signal being negated, and

wherein the output instruction is output when the first number of cycles of the clock signal lapses from the reception of the write data.

2. The device of claim 1 , further comprising:

a second circuit configured to generate a control signal whose logic changes based at least in part on the clock signal.

3. The device of claim 2 , wherein:

the control signal changes the logic when the first number of cycles of the clock signal lapses from the reception of the write data.

4. The device of claim 3 , wherein:

the first circuit further comprises a first generator configured to receive the control signal, output first to P th (P being a natural number of two or more) output timing signals, and make one of the first to P th timing signals a first level in every period in which the control signal is at a first level.

5. The device of claim 4 , wherein:

the control signal remains at the first level for a period whenever write data is being received by the memory device.

6. The device of claim 5 , wherein:

the first circuit further comprises a second generator configured to receive a second control signal, output first to Q th (Q being a natural number of two or more) start timing signals, and make one of the first to Q th start timing signals a first level in every period in which the second control signal is at a first level.

7. The device of claim 6 , wherein:

the first register is configured to receive the first start timing signal as the storing instruction, and receive the first output timing signal as the output instruction.

8. The device of claim 7 , further comprising:

second to n th registers configured to respectively receive the second to n th start timing signals, wherein the second to n th registers are configured to respectively receive the second to nth output timing signals, and

for each case of N (N being a natural number greater than or equal to two and lower than or equal to n) being two to n, the N th register is configured to latch a signal which the N th register is receiving at an input in response to reception of the N th start timing signal, and output the latched signal in response to reception of the N th output timing signal.

9. The device of claim 1 , wherein:

the first circuit comprises a second circuit and third circuits of a second number,

the second circuit outputs first signals of a third number,

the third number is smaller than the second number, and

one of the third circuits generates second signals of the second number from the first signals of the third number.

10. The device of claim 9 , wherein:

the second circuit generates the first signals of the third number from third signals of the second number.

11. The device of claim 9 , wherein:

the second circuit and one of the third circuits are coupled by interconnects of the third number.

12. A memory device comprising:

a memory cell which transitions to a first state or a second state by a first current flowing in the memory cell; and

a first circuit configured to stop supplying the first current when a first number of cycles of a clock signal lapses from reception of write data, and supply the first current based on a second number of cycles of the clock signal having passed after a read command is received by the memory device, the clock signal being input from outside the memory device.

13. The device of claim 12 , wherein:

the first circuit is configured to stop supplying the first current based on a third number of cycles of the clock signal having passed from the start of the supply of the first current.

14. The device of claim 13 , wherein:

the first circuit is configured to start supplying the first current when data stored in one of memory cells specified by the read command includes an error.

15. The device of claim 14 , wherein:

the first circuit is configured to supply the first current when the read command is received by the memory device after a first command.

16. The device of claim 12 , wherein:

the first circuit is configured to supply a second current when data stored in one of memory cells specified by a write command includes an error in response to completion of reception of the write data by the first circuit, and

the second current makes the one of memory cells a first state or a second state when the second current flows in the one of memory cells.

17. The device of claim 16 , wherein:

the first circuit is configured to supply the second current when the write command is received by the memory device after a first command.

18. A memory device comprising:

a memory cell which transitions to a first state or a second state by a first current flowing in the memory cell; and

a first circuit configured to start supplying the first current to the memory cell based on a write command being received by the memory device, and stop supplying the first current based on a timing which is based on a clock signal input from outside the memory device;

wherein the first circuit comprises:

a first register configured to store a signal received at an input of the first circuit in response to a storing instruction, and output the stored signal in response to an output instruction,

a pulse generator configured to negate a first signal based on a signal being output from the first register, and

a write circuit configured to stop supplying the first current by the first signal being negated, and

wherein the output instruction is based on the timing different from reception of the write command.