IP Library Granted Patent US 9,927,990
Granted Patent B2
US 9,927,990 · App. 15/066,298 · Granted Mar 27, 2018

Memory system, memory controller and memory control method

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Quick Facts
Patent No.
US 9,927,990
App. No.
15/066,298
Granted
Mar 27, 2018
Kind
B2
Abstract

According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.

Claims (52)

1. A memory system comprising:

a non-volatile memory;

an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and

a control unit that causes the encoding unit to encode k first data items among second data items and writes k third data items and fourth data items into the non-volatile memory, the second data items including n first data items, the k being an integer larger than or equal to zero and smaller than or equal to n, the n being an integer larger than or equal to two, the k third data items being obtained by the encoding unit, the fourth data items being obtained by removing data corresponding to the k third data items from the second data items, each of the k third data items being generated by encoding each of the k first data items with the encoding unit.

2. The memory system according claim 1 , further comprising:

an encoding control unit that determines a value of the k such that a total data length of the k third data items and the fourth data items is shorter than or equal a certain length, and a data length of the fourth data items is minimized.

3. The memory system according to claim 1 ,

wherein, when the control unit performs a second writing after a first writing, the control unit writes new k third data items and fourth data items from a position different from a writing-start position in the first writing in a certain memory region, the first writing being writing the k third data items and the fourth data items into the certain memory region in the non-volatile memory, the second writing including deleting the k third data items and the fourth data items and writing the new k third data items and fourth data items into the certain memory region.

4. The memory system according to claim 1 ,

wherein the encoding unit includes:

a plurality of encoders including encoding schemes different from one another; and

an encoding control unit that selects an encoder among the encoders such that a total data length of the k third data items and the fourth data items is shorter than or equal to a certain data length, and a data length of the fourth data items is minimized.

5. The memory system according to claim 1 , further comprising:

an error correction encoder that encodes the k third data items and the fourth data items with error correction encoding,

wherein the control unit writes the k third data items and the fourth data items encoded with the error correction encoding into the non-volatile memory.

6. The memory system according to claim 1 ,

wherein the second data items are randomized data.

7. The memory system according to claim 1 ,

wherein the encoding is Reverse Huffman coding, Reverse Tunstall coding, or Reverse Tunstall Huffman coding.

8. The memory system according to claim 1 , being connectable to a host,

wherein the second data item is data designated by a write request received from the host.

9. A memory controller that controls a non-volatile memory, the memory controller comprising:

an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and

a control unit that causes the encoding unit to encode k first data items among second data items and writes k third data items and fourth data items into the non-volatile memory, the second data items including n first data items, the k being an integer larger than or equal to zero and smaller than or equal to n, the n being an integer larger than or equal to two, the k third data items being obtained by the encoding unit, the fourth data items being obtained by removing data corresponding to the k third data items from the second data items, each of the k third data items being generated by encoding each of the k first data items with the encoding unit.

10. The memory controller according to claim 9 , further comprising:

an encoding control unit that determines a value of the k such that a total data length of the k third data items and the fourth data items is shorter than or equal to a certain data length, and a data length of the fourth data items is minimized.

11. The memory controller according to claim 9 ,

wherein, when the control unit performs a second writing after a first writing, the control unit writes new k third data items and fourth data items from a position different from a writing-start position in the first writing in a certain memory region, the first writing being writing the k third data items and the fourth data items into the certain memory region in the non-volatile memory, the second writing including deleting the k third data items and the fourth data items and writing the new k third data items and fourth data items into the certain memory region.

12. The memory controller according to claim 9 ,

wherein the encoding unit includes:

a plurality of encoders including encoding schemes different from one another; and

an encoding control unit that selects an encoder among the encoders such that a total data length of the k third data items and the fourth data items is shorter than or equal to a certain data length, and a data length of the fourth data items is minimized.

13. The memory controller according to claim 9 , further comprising:

an error correction encoder that encodes the k third data items and the fourth data items h error correction encoding,

wherein the control unit writes the k third data items and the fourth data items encoded with the error correction encoding into the non-volatile memory.

14. A non-volatile memory control method, the method comprising:

encoding k first data items among second data items, the encoding being encoding to generate a code word in which zero and one occur at different occurrence rates; and

writing k third data items and fourth data items into a non-volatile memory, the second data items including n first data items, the k being an integer larger than or equal to zero and smaller than or equal to n, the n being an integer larger than or equal to two, the k third data items being obtained by encoding k second data items among first data items including n second data items and having a first data length, the fourth data items being obtained by removing data corresponding to the k third data items from the second data items, each of the k third data items being generated by encoding each of the k first items with encoders.

15. The method according to claim 14 , further comprising:

determining a value of the k such that a total data length of the k third data items and the fourth data items is shorter than or equal to a certain data length, and a data length of the fourth data items is minimized.

16. The method according to claim 14 , further comprising:

writing, when a second writing is performed after a first writing, new k third data items and fourth data items from a position different from a writing-start position in the first writing in a certain memory region, the first writing being writing the k third data items and the fourth data items into the certain memory region in the non-volatile memory, the second writing including deleting the k third data items and the fourth data items and writing the new k third data items and fourth data items into the certain memory region.

17. The method according to claim 14 , further comprising:

performing the encoding with a plurality of encoding schemes; and

selecting an encoding scheme among the encoding schemes such that a total data length of the k third data items and the fourth data items is shorter than or equal to a certain data length, and data length of the fourth data items is minimized.

18. The method according to claim 14 , further comprising:

encoding the k third data items and the fourth data items with error correction encoding; and

writing the k third data items and fourth data items encoded with the error correction encoding into the non-volatile memory.

19. The method according to claim 14 ,

wherein the second data items are randomized data.

20. The method according to claim 14 ,

wherein the encoding is Reverse Huffman coding, Reverse Tunstall coding, or Reverse Tunstall Huffman coding.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043088/0620 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2016
From: TORII, OSAMU; HARA, TOKUMASA; UCHIKAWA, HIRONORI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 038188/0649 →