Semiconductor memory capable of reading data without accessing memory cell

1. A semiconductor memory comprising:

a first memory cell stably storing data after a first time from an end of a write operation;

a buffer latching the data in the write operation; and

a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first memory cell is executed, wherein the first read operation is an operation for the first memory cell, and the first read operation is an operation reading the data from the buffer without accessing the first memory cell.

2. The memory of claim 1 , wherein:

the first memory cell comprises a magnetoresistive element including a storage layer, a reference layer, an insulating layer between the storage layer and the reference layer, a shift cancelling layer, and a conductive layer between the reference layer and the shift cancelling layer, and

the reference layer and the shift cancelling layer are SAF-coupled each other.

3. The memory of claim 2 , wherein a magnetization direction of the reference layer is stable after the first time from the end of the write operation.

4. The memory of claim 2 , wherein the data is stored in the first memory cell by directing magnetization directions of the storage layer and the reference layer to opposite directions.

5. The memory of claim 2 , wherein magnetization directions of the storage layer, the reference layer and the shift cancelling layer direct to a direction in which the storage layer, the reference layer and the shift cancelling layer are stacked.

6. The memory of claim 1 , wherein the first time from the end of the write operation is longer than a second time from the end of the write operation to a start of the first read operation.

7. The memory of claim 1 , wherein the control circuit controls a second read operation when the second read operation is executed right after the first read operation is executed, wherein the first read operation is an operation for a second memory cell other than the first memory cell, the second read operation is an operation for the first memory cell, the second read operation is an operation reading the data from the first memory cell, and the first time is shorter than a sum of a second time from the end of the write operation to a start of the first read operation and a third time from the start of the first read operation to an end of the first read operation.

8. The memory of claim 7 , wherein the control circuit comprises a trimming portion optimizing the second and third times by a control signal.

9. The memory of claim 1 , wherein the control circuit comprises an address latch portion latching a first address of the first memory cell in the write operation, a comparator comparing a second address of the first read operation with the first address latched in the address latch portion in the first read operation, and a processing portion controlling the first read operation based on an output signal of the comparator.

10. The memory of claim 1 , wherein the buffer latches data of memory cells accessed by one read/write command.

11. A semiconductor memory comprising:

a first magnetoresistive element stably storing data after a first time from an end of a write operation;

a buffer latching the data in the write operation; and

a control circuit controlling a first read operation when the first read operation is executed right after the write operation for the first magnetoresistive element is executed, wherein the first read operation is an operation for the first magnetoresistive element, and the first read operation is an operation reading the data from the buffer without accessing the first magnetoresistive element.

12. The memory of claim 11 , wherein:

the first magnetoresistive element includes a storage layer, a reference layer, an insulating layer between the storage layer and the reference layer, a shift cancelling layer, and a conductive layer between the reference layer and the shift cancelling layer, and

the reference layer and the shift cancelling layer are SAF-coupled each other.

13. The memory of claim 12 , wherein a magnetization direction of the reference layer is stable after the first time from the end of the write operation.

14. The memory of claim 12 , wherein the data is stored in the first magnetoresistive element by directing magnetization directions of the storage layer and the reference layer to opposite directions.

15. The memory of claim 12 , wherein magnetization directions of the storage layer, the reference layer and the shift cancelling layer direct to a direction in which the storage layer, the reference layer and the shift cancelling layer are stacked.

16. The memory of claim 11 , wherein the first time from the end of the write operation is longer than a second time from the end of the write operation to a start of the first read operation.

17. The memory of claim 11 , wherein the control circuit controls a second read operation when the second read operation is executed right after the first read operation is executed, wherein the first read operation is an operation for a second magnetoresistive element other than the first magnetoresistive element, the second read operation is an operation for the first magnetoresistive element, the second read operation is an operation reading the data from the first magnetoresistive element, and the first time is shorter than a sum of a second time from the end of the write operation to a start of the first read operation and a third time from the start of the first read operation to an end of the first read operation.

18. The memory of claim 17 , wherein the control circuit comprises a trimming portion optimizing the second and third times by a control signal.

19. The memory of claim 11 , wherein the control circuit comprises an address latch portion latching a first address of the first magnetoresistive element in the write operation, a comparator comparing a second address of the first read operation with the first address latched in the address latch portion in the first read operation, and a processing portion controlling the first read operation based on an output signal of the comparator.

20. The memory of claim 11 , wherein the buffer latches data of magnetoresistive elements accessed by one read/write command.