IP Library Granted Patent US 9,519,491
Granted Patent B2
US 9,519,491 · App. 15/067,045 · Granted Dec 13, 2016

Time monitoring in a processing element and use

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Quick Facts
Patent No.
US 9,519,491
App. No.
15/067,045
Granted
Dec 13, 2016
Kind
B2
Abstract

System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread

Claims (42)

1. A system comprising:

a processing element, comprising:

a clock;

a thread suspend/resume logic block, configured to suspend execution of a thread without interrupting the processing element and in response to a received suspend thread instruction;

a local reference clock, coupled to the processing element and to a peripheral device, wherein the peripheral device is configured to provide a global time to the processing element; and

a time monitor circuit (TMC), wherein the TMC is configured to:

receive an indication of a wakeup time;

discipline the clock via adjustment of the global time based on a difference between a local reference time and a subsequent local reference time, thereby compensating for latency due to the provision of the global time by the software, wherein the subsequent local reference time is retrieved from the local reference clock, wherein the global time is provided by software, and wherein to provide the global time, the software is executable to:

retrieve the local reference time from the local reference clock that corresponds to the global time; and

provide the global time and the local reference time to the processing element;

monitor time via the clock until the wakeup time obtains; and

invoke the thread suspend/resume logic block to resume execution of the thread in response to the wakeup time obtaining.

2. The system of claim 1 , wherein the indication of the wakeup time is an absolute time.

3. The system of claim 1 , wherein the indication of the wakeup time is a relative time.

4. The system of claim 1 , wherein the local reference clock is connected directly to the processing element and the peripheral device.

5. The system of claim 1 , wherein an external time source comprises an external hardware signal, wherein the external hardware signal comprises an epoch and a clock signal.

6. A method, comprising:

receiving an indication of a wakeup time to a time monitoring circuit (TMC) comprised in a processing element;

suspending execution of a thread without interrupting the processing element via a thread suspend/resume logic block comprised in the processing element in response to a received suspend thread instruction;

disciplining a clock comprised in the processing element via adjustment of a global time based on a difference between a local reference time and a subsequent local reference time, thereby compensating for latency due to the provision of the global time by the software, wherein the subsequent local reference time is retrieved from a local reference clock comprised in the processing element, wherein the global time is provided by software, and wherein to provide the global time, the software is executable to:

retrieve the local reference time from the local reference clock that corresponds to the global time; and

provide the global time and the local reference time to the processing element;

monitoring time, via the TMC using a clock comprised in the processing element, until the wakeup time obtains; and

invoking the thread suspend/resume logic block via the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread.

7. The method of claim 6 , wherein the indication of the wakeup time is an absolute time.

8. The method of claim 6 , wherein the indication of the wakeup time is a relative time.

9. The method of claim 6 , wherein the local reference clock is connected directly to the processing element and the peripheral device.

10. The method of claim 6 , wherein an external time source comprises an external hardware signal, wherein the external hardware signal comprises an epoch and a clock signal.

11. A system comprising:

a processing element, comprising:

a clock;

a thread suspend/resume logic block, configured to suspend execution of a thread in response to a received suspend thread instruction; and

a time monitor circuit (TMC); and

a local reference clock, connected directly to the processing element and to a network interface controller (NIC);

wherein the TMC is configured to:

receive an indication of a wakeup time;

discipline the clock via adjustment of the global time based on a difference between a local reference time and a subsequent local reference time, thereby compensating for latency due to the provision of the global time by the software, wherein the subsequent local reference time is retrieved from the local reference clock, wherein the global time is provided by software, and wherein to provide the global time, the software is executable to:

retrieve the local reference time from the local reference clock that corresponds to the global time; and

provide the global time and the local reference time to the processing element;

monitor time via the clock until the wakeup time obtains; and

invoke the thread suspend/resume logic block to resume execution of the thread in response to the wakeup time obtaining.

12. The system of claim 11 , wherein an external time source comprises an external hardware signal, wherein the external hardware signal comprises an epoch and a clock signal.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →